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    • 1. 发明授权
    • Signal pattern recognition apparatus comprising parameter training
controller for training feature conversion parameters and discriminant
functions
    • 信号模式识别装置,包括用于训练特征转换参数和判别函数的参数训练控制器
    • US5754681A
    • 1998-05-19
    • US493719
    • 1995-06-22
    • Hideyuki WatanabeTsuyoshi YamaguchiShigeru Katagiri
    • Hideyuki WatanabeTsuyoshi YamaguchiShigeru Katagiri
    • G06K9/66G06F15/18G06K9/62G06N3/00G06T7/00G10L15/02G10L15/08G10L15/10G10L15/20G10L21/02
    • G06K9/6247G06K9/6215
    • In a signal pattern recognition apparatus, a plurality of feature transformation sections respectively transform an inputted signal pattern into vectors in a plurality of feature spaces corresponding respectively to predetermined classes using a predetermined transformation parameter corresponding to each of the classes so as to emphasize a feature of each of the classes, and a plurality of discriminant function sections respectively calculates a value of a discriminant function using a predetermined discriminant function representing a similarity measure of each of the classes for the transformed vectors in the plurality of feature spaces. Then, a selection section executes a signal pattern recognition process by selecting a class to which the inputted signal pattern belongs based on the calculated values of a plurality of discriminant functions corresponding respectively to the classes, and a training control section trains and sets a plurality of transformation parameters of the feature transformation process and a plurality of discriminant functions so that an error probability of the signal pattern recognition is minimized based on a predetermined training signal pattern.
    • 在信号模式识别装置中,多个特征变换部分使用对应于每个类别的预定变换参数分别将输入的信号模式变换成分别对应于预定类别的多个特征空间中的向量,以便强调特征 各个类别和多个判别函数部分分别使用表示多个特征空间中的变换向量的各类的相似性度量的预定判别函数来计算判别函数的值。 然后,选择部根据分别对应于多个等级的多个判别函数的计算值,选择输入信号模式所属的等级,执行信号模式识别处理,训练控制部对多个 特征变换处理的变换参数和多个判别函数,使得基于预定的训练信号模式将信号模式识别的错误概率最小化。
    • 3. 发明授权
    • Pattern and speech recognition using accumulated partial scores from a
posteriori odds, with pruning based on calculation amount
    • 模式和语音识别使用累积的部分分数从后验赔率,根据计算量修剪
    • US5749069A
    • 1998-05-05
    • US405674
    • 1995-03-17
    • Takashi KomoriShigeru Katagiri
    • Takashi KomoriShigeru Katagiri
    • G10L15/10G10L15/00G10L15/08G10L15/28G10L5/06
    • G10L15/08G10L2015/085G10L2015/088
    • A speech recognition apparatus includes a data input portion to which input data which is a speech pattern is applied, a score calculation portion calculating a score indicating a possibility of recognition of a partial pattern of the speech pattern based on the estimate of a posteriori odds, an optimization design portion designing optimized parameters for calculating the estimate of the a posteriori odds in the score calculation portion and/or optimized parameters of pruning functions controlling calculation amount in the pruning processing portion, a pruning processing portion pruning the score for making operation efficient, an accumulated score calculating portion accumulating pruned scores to calculate an accumulated score, a recognition result decision portion classifying input data for every class based on the accumulated score and deciding a recognition result, and a recognition result output portion providing the recognition result.
    • 语音识别装置包括:应用了语音模式的输入数据的数据输入部,基于后验概率的估计,计算表示语音模式的部分模式的识别的可能性的分数的分数计算部, 设计用于计算分数计算部分的后验概率的估计的优化参数和/或控制修剪处理部分中计算量的修剪函数的优化参数的优化设计部分,修剪分数以使操作有效的修剪处理部分, 积累分数计算部分累积修剪得分以计算累积分数;识别结果判定部分,基于累积分数对所分类的输入数据进行分类并确定识别结果;以及识别结果输出部分,提供识别结果。
    • 4. 发明授权
    • Accelerator for mounting and interfacing a second CPU onto a motherboard
    • 用于将第二个CPU安装到主板上的加速器
    • US5687358A
    • 1997-11-11
    • US607548
    • 1996-02-27
    • Shinsuke SaitoShigeru Katagiri
    • Shinsuke SaitoShigeru Katagiri
    • G06F1/04G06F13/40
    • G06F13/4063G06F1/04
    • The present invention provides an accelerator working in place of a CPU on a motherboard to speed up the processing. The accelerator can realize the high-speed processing even when a clock on the accelerator is not an integral multiple of a clock on the CPU. When a clock frequency of a clock signal CLK on the motherboard is equal to 20 MHz and a maximum frequency of a CPU (3) on an accelerator (100) is equal to 33 MHz, for example, the CPU (3) does not work properly by a doubled clock signal. In such a case, a clock multiplication circuit (3a) multiplies the clock signal CLK by 1.5 times to generate a clock signal CLK15. There are three different patterns in the relationship between the timing of access of the CPU 3 and the timing of access of the motherboard. The accelerator of the invention determines the appropriate timing in each case and allows the access of the CPU 3 to be synchronous with the access of the motherboard.
    • 本发明提供一种用于代替主板上的CPU的加速器,以加速处理。 即使加速器上的时钟不是CPU上的时钟的整数倍,加速器也可以实现高速处理。 当母板上的时钟信号CLK的时钟频率等于20MHz,并且加速器(100)上的CPU(3)的最大频率等于33MHz时,CPU(3)不工作 正确地通过双倍时钟信号。 在这种情况下,时钟倍增电路(3a)将时钟信号CLK乘以1.5倍以产生时钟信号CLK15。 在CPU 3的访问定时与主板的访问时间之间的关系中存在三种不同的模式。 本发明的加速器在每种情况下确定适当的定时,并允许CPU 3的访问与主板的访问同步。