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1. 发明授权

US08569962B2 LED driver circuit and LED driver system 失效
标题翻译： LED驱动电路和LED驱动系统
公开(公告)号：US08569962B2
公开(公告)日：2013-10-29
申请号：US13233291
申请日：2011-09-15
申请人： Hideyuki Hagino , Masahiro Shimozono , Shinichi Kiyota
发明人： Hideyuki Hagino , Masahiro Shimozono , Shinichi Kiyota
IPC分类号： H05B37/00
CPC分类号： G09G3/3413 , G09G2320/064 , G09G2330/04
摘要： A withstand voltage of the LED driver circuit is set to be lower than an LED power supply voltage of the power supply and be higher than a first voltage value obtained by subtracting a voltage drop across whole of the LEDs connected in series caused by the second constant current from the LED power supply voltage.When raising a luminous intensity of the LEDs, in response to the control signal, the control circuit controls the switch circuit to bring about conduction between the LED drive terminal and the first switch terminal to let the first constant current flow through the LEDs.When lowering the luminous intensity of the LEDs, in response to the control signal, the control circuit controls the switch circuit to bring about conduction between the LED drive terminal and the second switch terminal to let the second constant current flow through the LEDs.
摘要翻译： LED驱动器电路的耐压设定为低于电源的LED电源电压，并且高于通过从第二常数减去串联连接的整个LED的电压降而获得的第一电压值电流从LED电源电压。当提高LED的发光强度时，响应于控制信号，控制电路控制开关电路以使LED驱动端子和第一开关端子之间导通，以使第一恒定电流流过LED。当降低LED的发光强度时，响应于控制信号，控制电路控制开关电路以在LED驱动端子和第二开关端子之间导通，以使第二恒定电流流过LED。

2. 发明申请

US20120139430A1 LED DRIVER CIRCUIT AND LED DRIVER SYSTEM 失效
标题翻译： LED驱动电路和LED驱动器系统
公开(公告)号：US20120139430A1
公开(公告)日：2012-06-07
申请号：US13233291
申请日：2011-09-15
申请人： Hideyuki Hagino , Masahiro Shimozono , Shinichi Kiyota
发明人： Hideyuki Hagino , Masahiro Shimozono , Shinichi Kiyota
IPC分类号： H05B37/02
CPC分类号： G09G3/3413 , G09G2320/064 , G09G2330/04
摘要： A withstand voltage of the LED driver circuit is set to be lower than an LED power supply voltage of the power supply and be higher than a first voltage value obtained by subtracting a voltage drop across whole of the LEDs connected in series caused by the second constant current from the LED power supply voltage.When raising a luminous intensity of the LEDs, in response to the control signal, the control circuit controls the switch circuit to bring about conduction between the LED drive terminal and the first switch terminal to let the first constant current flow through the LEDs.When lowering the luminous intensity of the LEDs, in response to the control signal, the control circuit controls the switch circuit to bring about conduction between the LED drive terminal and the second switch terminal to let the second constant current flow through the LEDs.
摘要翻译： LED驱动器电路的耐压设定为低于电源的LED电源电压，并且高于通过从第二常数减去串联连接的整个LED的电压降而获得的第一电压值电流从LED电源电压。当提高LED的发光强度时，响应于控制信号，控制电路控制开关电路以使LED驱动端子和第一开关端子之间导通，以使第一恒定电流流过LED。当降低LED的发光强度时，响应于控制信号，控制电路控制开关电路以在LED驱动端子和第二开关端子之间导通，以使第二恒定电流流过LED。

3. 发明授权

US5548679A Digital PLL system 失效
标题翻译：数字PLL系统
公开(公告)号：US5548679A
公开(公告)日：1996-08-20
申请号：US386656
申请日：1995-02-10
申请人： Shinichi Kiyota
发明人： Shinichi Kiyota
IPC分类号： H02P29/00 , H02P7/29 , H02P23/00 , H03L7/06 , H02P5/17
CPC分类号： H02P23/22 , Y10S388/911 , Y10S388/912
摘要： A PLL system has a phase comparator for converting the phase difference between a reference clock signal and a feedback clock signal corresponding to a PWM signal Into a binary value, a frequency comparator for converting the frequency difference between the reference and feedback clock signals into a binary value, an automatic gain controller for adjusting the loop gain of the PLL system to a given value whenever the output of the frequency comparator reaches a change point, and a PWM signal generator for generating the PWM signal according to the outputs of the phase comparator, frequency comparator, and automatic gain controller. These components of the PLL system process digital signals, to simplify the structure of the PLL system, expand the range of loop gains to be set, and speedily synchronize the feedback clock signal with the reference clock signal.
摘要翻译： PLL系统具有用于将参考时钟信号和对应于PWM信号的反馈时钟信号之间的相位差转换为二进制值的相位比较器，用于将参考和反馈时钟信号之间的频率差转换为二进制值的二进制值值，每当频率比较器的输出达到变化点时，将PLL系统的环路增益调整到给定值的自动增益控制器和用于根据相位比较器的输出产生PWM信号的PWM信号发生器，频率比较器和自动增益控制器。 PLL系统的这些组件处理数字信号，以简化PLL系统的结构，扩大要设置的环路增益范围，并使反馈时钟信号与参考时钟信号快速同步。

4. 发明授权

US5402009A Pulse generator for generating a variable-width pulse having a small delay 失效
标题翻译：用于产生具有小延迟的可变宽度脉冲的脉冲发生器
公开(公告)号：US5402009A
公开(公告)日：1995-03-28
申请号：US86097
申请日：1993-07-06
申请人： Shinichi Kiyota
发明人： Shinichi Kiyota
IPC分类号： G06F1/025 , H03K5/05 , H03K7/04 , H03K5/04
CPC分类号： G06F1/025 , H03K5/05 , H03K7/04
摘要： A pulse generator has a presetting clock synchronous counter having a count enable terminal, the counter which counts up input data using a clock signal whose basic unit of time width corresponds to its one period. The output from said counter is decoded to produce a first state signal. A second state signal is produced from said clock signal and a count enable signal for said counter. An output pulse having a desired pulse width is obtained by calculating the logical product of said first and second state signals.
摘要翻译：脉冲发生器具有具有计数使能端的预置时钟同步计数器，该计数器使用其基本时间宽度对应于其一个周期的时钟信号对输入数据进行计数。来自所述计数器的输出被解码以产生第一状态信号。从所述时钟信号和所述计数器的计数使能信号产生第二状态信号。通过计算所述第一和第二状态信号的逻辑积，获得具有期望脉冲宽度的输出脉冲。

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