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1. 发明授权

US08754632B2 Integrated circuit with power state determination circuit 有权
标题翻译：具有电源状态确定电路的集成电路
公开(公告)号：US08754632B2
公开(公告)日：2014-06-17
申请号：US13159543
申请日：2011-06-14
申请人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
IPC分类号： G01R19/00
CPC分类号： H01L27/0274 , G01R31/026 , G01R31/2884
摘要： An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
摘要翻译：形成有电源端子，接地端子，输入端子和内部电路的集成电路具有从输入端子到电源端子的方向的单向电路，单向电路设置在输入端子和电源端子; 以及电源状态确定电路，其检测电源端子是否连接到外部电源以输出电源打开检测信号。单向电路包括：第一晶体管，其中电源端子的电压施加到栅极;以及第二晶体管，其串联连接到第一晶体管，并且外部电源的电压被输入到输入端子。

2. 发明申请

US20120074926A1 INTEGRATED CIRCUIT WITH POWER STATE DETERMINATION CIRCUIT 有权
标题翻译：集成电路与电源状态确定电路
公开(公告)号：US20120074926A1
公开(公告)日：2012-03-29
申请号：US13159543
申请日：2011-06-14
申请人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Takayuki Nagasawa , Hideaki Suzuki
IPC分类号： G01R19/00
CPC分类号： H01L27/0274 , G01R31/026 , G01R31/2884
摘要： An integrated circuit in which a power terminal, a ground terminal, an input terminal and an internal circuit are formed, has a unidirectional circuit of a direction from the input terminal to the power terminal, the unidirectional circuit being provided between the input terminal and the power terminal; and a power state determination circuit which detects whether the power terminal is connected to an external power source or not to output a power open detection signal. And the unidirectional circuit includes a first transistor in which a voltage of the power terminal is applied to a gate, and a second transistor connected to the first transistor in series, and a voltage of the external power source is input to the input terminal.
摘要翻译：形成有电源端子，接地端子，输入端子和内部电路的集成电路具有从输入端子到电源端子的方向的单向电路，单向电路设置在输入端子和电源端子; 以及电源状态确定电路，其检测电源端子是否连接到外部电源以输出电源打开检测信号。单向电路包括：第一晶体管，其中电源端子的电压施加到栅极;以及第二晶体管，其串联连接到第一晶体管，并且外部电源的电压被输入到输入端子。

3. 发明授权

US07603248B2 Testing circuit and testing method for semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片的测试电路和测试方法
公开(公告)号：US07603248B2
公开(公告)日：2009-10-13
申请号：US11474393
申请日：2006-06-26
申请人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
IPC分类号： G06F19/00
CPC分类号： G01R31/31719 , G01R31/31701 , G01R31/31721
摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
摘要翻译：一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。划片PAD和划线ROM形成在晶片的切割区域中。在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位或否定。

4. 发明授权

US07750437B2 Semiconductor device having a diode for a rectifier circuit 有权
标题翻译：具有用于整流电路的二极管的半导体器件
公开(公告)号：US07750437B2
公开(公告)日：2010-07-06
申请号：US11229161
申请日：2005-09-19
申请人： Hideaki Suzuki , Hidetoshi Sugiyama
发明人： Hideaki Suzuki , Hidetoshi Sugiyama
IPC分类号： H01L29/93
CPC分类号： H01L27/0814 , H01L21/761 , H01L27/0823
摘要： A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
摘要翻译：半导体器件在第一导电类型的半导体衬底上具有整流电路和集成电路，并且在衬底中具有第一阱区域，第一阱区域中的第二阱区域和形成在第二阱区域中的二极管区域，并且构成具有第二阱区的二极管。整流电路由二极管形成。在正和负电位之间变化的输入电源端子连接到第一二极管的第二和第一阱区域以及第二二极管的二极管区域。电流源端子设置在第一二极管的第一阱区附近，并且连接到衬底和规定的电源，以便当第一阱区和半导体衬底之间的PN结提供电流时输入电源端子处于负电位。

5. 发明申请

US20070203662A1 Testing circuit and testing method for semiconductor device and semiconductor chip 有权
标题翻译：半导体器件和半导体芯片的测试电路和测试方法
公开(公告)号：US20070203662A1
公开(公告)日：2007-08-30
申请号：US11474393
申请日：2006-06-26
申请人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
发明人： Hidetoshi Sugiyama , Masao Nakajima , Haruyuki Mouri , Hideaki Suzuki
IPC分类号： G06F19/00
CPC分类号： G01R31/31719 , G01R31/31701 , G01R31/31721
摘要： A testing circuit for a semiconductor device having a test mode in which the information about built-in memory cannot be read after conducting a test on a semiconductor device, and cutting a pad formed in a scribe area is provided. The scribe PAD and the scribe ROM are formed in the cutting area of a wafer. Upon power-up of a chip a, the power-on reset circuit transmits a reset signal to the mode register. After setting the initial resister value to “00”, a mode switch signal is input from the mode switch terminal, the scribe ROM is activated, and the test mode is set. In this process, a Manchester coded signal is provided from the scribe PAD, decoded by a clock of dividing frequency provided from the clock dividing circuit, the value of the register in the test mode in the mode register is set, and external reset is asserted or negated.
摘要翻译：一种半导体器件的测试电路，具有测试模式，其中在对半导体器件进行测试之后无法读取关于内置存储器的信息，并且切割形成在划线区域中的焊盘。划片PAD和划线ROM形成在晶片的切割区域中。在芯片a上电时，上电复位电路将复位信号发送到模式寄存器。将初始电阻值设置为“00”后，从模式开关端子输入模式切换信号，激活划线ROM，并设置测试模式。在这个过程中，曼彻斯特编码信号由划片PAD提供，由时钟分频电路提供的分频时钟解码，设置模式寄存器中的测试模式中的寄存器的值，并且断言外部复位或否定。

6. 发明申请

US20060273403A1 Semiconductor device having a diode for a rectifier circuit 有权
标题翻译：具有用于整流电路的二极管的半导体器件
公开(公告)号：US20060273403A1
公开(公告)日：2006-12-07
申请号：US11229161
申请日：2005-09-19
申请人： Hideaki Suzuki , Hidetoshi Sugiyama
发明人： Hideaki Suzuki , Hidetoshi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L27/0814 , H01L21/761 , H01L27/0823
摘要： A semiconductor device has a rectifier circuit and integrated circuit on a semiconductor substrate of a first conduction type, and has a first well region in the substrate, a second well region in first well region, and a diode region formed in second well region and constituting a diode with second well region. The rectifier circuit is formed by the diodes. An input power supply terminal, changing between positive and negative potentials, is connected to second and first well regions of a first diode and to diode region of a second diode. A current supply terminal is provided in the vicinity of first well region of first diode, and is connected to the substrate and a prescribed power supply, so as to supply a current to the PN junction between the first well region and the semiconductor substrate when the input power supply terminal is at negative potential.
摘要翻译：半导体器件在第一导电类型的半导体衬底上具有整流电路和集成电路，并且在衬底中具有第一阱区域，第一阱区域中的第二阱区域和形成在第二阱区域中的二极管区域，并且构成具有第二阱区的二极管。整流电路由二极管形成。在正和负电位之间变化的输入电源端子连接到第一二极管的第二和第一阱区域以及第二二极管的二极管区域。电流源端子设置在第一二极管的第一阱区附近，并且连接到衬底和规定的电源，以便当第一阱区和半导体衬底之间的PN结提供电流时输入电源端子处于负电位。

7. 发明授权

US11936825B2 Image forming apparatus using an adjustment pattern formed on one side of a medium to correct image formation on the opposite side of the medium 有权
公开(公告)号：US11936825B2
公开(公告)日：2024-03-19
申请号：US18101199
申请日：2023-01-25
申请人： Hideaki Suzuki
发明人： Hideaki Suzuki
IPC分类号： H04N1/00 , H04N1/19
CPC分类号： H04N1/00588 , H04N1/1903 , H04N2201/3242
摘要： An image forming apparatus includes a conveyor, an image former, and a reading device. The conveyor conveys a medium in a conveyance direction. The image former forms an adjustment pattern on one side of the medium conveyed by the conveyor. The reading device downstream from the image former in the conveyance direction reads the adjustment pattern on the one side of the medium conveyed by the conveyor to generate read data. The adjustment pattern includes a first line segment and a second line segment that extend in directions different from each other and each are inclined with respect to the conveyance direction.

8. 外观设计

USD795141S1 Rear bumper for a motor vehicle 有权
公开(公告)号：USD795141S1
公开(公告)日：2017-08-22
申请号：US29582827
申请日：2016-10-31
申请人： Gen Ikeda , Hideaki Suzuki
设计人： Gen Ikeda , Hideaki Suzuki

9. 发明授权

US09376467B2 Cross-linked peptides containing non-peptide cross-linked structure, method for synthesizing cross-linked peptides, and novel organic compound used in method 有权
公开(公告)号：US09376467B2
公开(公告)日：2016-06-28
申请号：US14004058
申请日：2012-02-28
申请人： Yusuke Kono , Shuji Fujita , Hideaki Suzuki , Mari Okumoto , Takashi Nakae , Kazuhiro Chiba
发明人： Yusuke Kono , Shuji Fujita , Hideaki Suzuki , Mari Okumoto , Takashi Nakae , Kazuhiro Chiba
IPC分类号： C07K7/08 , A61K47/48 , C07K1/00 , C07K1/113 , C07K7/06 , C07K14/00
CPC分类号： C07K7/08 , A61K38/00 , A61K47/60 , C07K1/006 , C07K1/061 , C07K1/113 , C07K7/06 , C07K14/00
摘要： The purpose of the present invention is to provide a cross-linked peptide containing a novel non-peptide cross-linked structure, and a method for synthesizing the same. A cross-linked peptide having a novel non-peptide cross-linked structure, a useful intermediate for synthesizing the cross-linked peptide, and a method for synthesizing the novel cross-linked peptide and the intermediate are provided. The cross-linked peptide is characterized by having an —NR— bond in the cross-linked structure. By using the method for synthesizing the cross-linked peptide, a cross-link can be freely designed and an change can be freely made to a cross-link.

10. 发明授权

US09292011B2 Operating machine and maintenance and inspection information generating apparatus 有权
标题翻译：操作机维修检查信息生成装置
公开(公告)号：US09292011B2
公开(公告)日：2016-03-22
申请号：US14113633
申请日：2012-04-24
申请人： Hideaki Suzuki , Kozo Nakamura , Shinya Yuda , Hiroki Uchiyama , Takashi Saeki , Kesaaki Minemura , Jyunsuke Fujiwara
发明人： Hideaki Suzuki , Kozo Nakamura , Shinya Yuda , Hiroki Uchiyama , Takashi Saeki , Kesaaki Minemura , Jyunsuke Fujiwara
IPC分类号： G05B15/02 , E02F9/26 , G06Q10/00
CPC分类号： G05B15/02 , E02F9/267 , G06Q10/20
摘要： A hydraulic shovel includes: a storage unit which stores an operation history of a target component of the shovel targeted for life span estimation, a discrimination threshold value used for classifying usage of the target component into a plurality of usage modes based on the operation history, and a usage mode-specific estimated life span indicative of an estimated life span of the target component in each of the usage modes; and an arithmetic and control unit which calculates an operating time of the target component in each of the usage modes in accordance with the operation history and the discrimination threshold value, and estimates the life span of the target component based on the operating time calculated for each of the usage modes and on the usage mode-specific estimated life span.
摘要翻译：液压挖掘机包括：存储单元，其存储针对寿命估计的铲的目标分量的操作历史;基于操作历史将用于将目标分量的使用分类为多个使用模式的鉴别阈值，以及指示每个使用模式中目标组件的估计使用寿命的使用模式特定估计寿命; 以及算术和控制单元，其根据操作历史和鉴别阈值来计算每个使用模式中的目标分量的操作时间，并且基于针对每个使用模式计算的操作时间来估计目标分量的寿命的使用模式和使用模式特定的估计寿命。

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