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1. 发明授权

US06404592B1 Magnetic head producing method 有权
标题翻译：磁头制作方法
公开(公告)号：US06404592B1
公开(公告)日：2002-06-11
申请号：US09626948
申请日：2000-07-27
申请人： Hidetoshi Saito , Tomoo Otsuka , Masahiro Iizuka
发明人： Hidetoshi Saito , Tomoo Otsuka , Masahiro Iizuka
IPC分类号： G11B560
CPC分类号： G11B21/21 , G11B5/4826 , G11B5/60 , Y10T29/49052
摘要： An improved magnetic head includes a slider and a thin film element, the later of which is provided on a trailing side of the slider. The slider has core layers. The surfaces of the core layers are abraded so that the thickness of an &agr; phase constituting the, surface structures of the core layers may be reduced to a very small value. In this way, even if a carbon film is directly formed on the core layers, it is still possible to ensure a desired diffusion between the carbon film and the &agr; phase, which effectively prevents the carbon film from separation (peeling) and avoiding the formation of any spot on the carbon film.
摘要翻译：改进的磁头包括滑块和薄膜元件，其后面设置在滑块的后侧。滑块具有核心层。芯层的表面被磨损，使得构成芯层的表面结构的α相的厚度可以被减小到非常小的值。以这种方式，即使在芯层上直接形成碳膜，也可以确保碳膜和α相之间的期望的扩散，有效地防止碳膜分离（剥离）并避免形成在碳膜上的任何点。

2. 发明授权

US06271994B1 Magnetic head having a thin film element 有权
标题翻译：具有薄膜元件的磁头
公开(公告)号：US06271994B1
公开(公告)日：2001-08-07
申请号：US09159326
申请日：1998-09-23
申请人： Hidetoshi Saito , Tomoo Otsuka , Masahiro Iizuka
发明人： Hidetoshi Saito , Tomoo Otsuka , Masahiro Iizuka
IPC分类号： G11B2121
CPC分类号： G11B21/21 , G11B5/4826 , G11B5/60 , Y10T29/49052
摘要： An improved magnetic head comprises a slider and a thin film element, the later of which is provided on a trailing side of the slider. The slider has core layers. The surfaces of the core layers are abraded so that the thickness of an a phase constituting the surface structures of the core layers may be reduced to a very small value. In this way, even if a carbon film is directly formed on the core layers, it is still possible to ensure a desired diffusion between the carbon film and the a phase, thereby effectively preventing the carbon film from separation (peeling) and avoiding the formation of any spot on the carbon film.
摘要翻译：改进的磁头包括滑块和薄膜元件，其后面设置在滑块的后侧。滑块具有核心层。芯层的表面被磨损，使得构成芯层的表面结构的a相的厚度可以减小到非常小的值。这样，即使在芯层上直接形成碳膜，也可以确保碳膜与a相之间的期望的扩散，从而有效地防止碳膜分离（剥离）并避免形成在碳膜上的任何点。

3. 发明授权

US08649234B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US08649234B2
公开(公告)日：2014-02-11
申请号：US13285181
申请日：2011-10-31
申请人： Toshifumi Watanabe , Hidetoshi Saito
发明人： Toshifumi Watanabe , Hidetoshi Saito
IPC分类号： G11C7/00
CPC分类号： G11C7/222 , G11C16/10 , G11C16/32
摘要： According to one embodiment, an interface includes first to third input circuits, delay and selection circuits. The first input circuit outputs an active first internal signal in response to an active first control signal received by a memory device. The second input circuit outputs an active second internal signal in response to an active second control signal received by the device while the device is receiving the active first control signal. The delay circuit outputs a selection signal in first or second states after the elapse of a first period from inactivation or activation of the first control signal. The selection circuit outputs the first and second internal signals as an enable signal while receiving the selection signal of the first and second states. The third input circuit outputs an input signal received from the outside from the interface to inside the device while receiving the active enable signal.
摘要翻译：根据一个实施例，接口包括第一至第三输入电路，延迟和选择电路。第一输入电路响应于由存储器件接收到的有效的第一控制信号而输出有效的第一内部信号。第二输入电路响应于设备在接收到有效的第一控制信号时接收到的有效的第二控制信号而输出有效的第二内部信号。延迟电路在从第一控制信号的失活或激活开始经过第一周期之后，输出第一或第二状态的选择信号。选择电路在接收第一和第二状态的选择信号的同时，将第一和第二内部信号作为使能信号输出。第三输入电路在接收到有效使能信号的同时，将从外部接收的输入信号输出到设备内部。

4. 发明授权

US08542184B2 Driving device and driving method of electrophoretic display 失效
标题翻译：电泳显示器的驱动装置和驱动方法
公开(公告)号：US08542184B2
公开(公告)日：2013-09-24
申请号：US12637020
申请日：2009-12-14
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G09G3/34
CPC分类号： G09G3/344 , G09G2310/0275 , G09G2310/0289 , G09G2310/06 , G09G2370/08
摘要： A driving device of an electrophoretic display panel having a common electrode and a plurality of divided electrodes disposed opposite to the common electrode includes: a first driving circuit that outputs a plurality of voltages corresponding to a plurality of voltage data supplied as a series of data and supplies the plurality of voltages to the plurality of divided electrodes; and a second driving circuit that outputs a voltage corresponding to supplied data and supplies the voltage to the common electrode.
摘要翻译：具有公共电极和与公共电极相对设置的多个分割电极的电泳显示面板的驱动装置包括：第一驱动电路，其输出与作为一系列数据提供的多个电压数据相对应的多个电压;以及将多个电压提供给所述多个分割电极; 以及第二驱动电路，其输出与所提供的数据相对应的电压，并将电压提供给公共电极。

5. 发明授权

US08400376B2 Voltage selection circuit, electrophoretic display apparatus, and electronic device 有权
标题翻译：电压选择电路，电泳显示装置和电子装置
公开(公告)号：US08400376B2
公开(公告)日：2013-03-19
申请号：US12366103
申请日：2009-02-05
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G09G3/30
CPC分类号： G09G3/344 , G09G2300/0814 , Y10T307/696
摘要： Provided is a voltage selection circuit for outputting a potential selected from a plurality of input potentials, the voltage selection circuit capable of selectively outputting a first high-level potential being a highest potential, a second high-level potential, or a third high-level potential being a lowest potential from an output terminal thereof. The voltage selection circuit includes a first switching circuit that supplies the first high-level potential to the output terminal, a second switching circuit that supplies the second high-level potential to the output terminal, and a third switching circuit that supplies the third high-level potential to the output terminal. The first switching circuit includes a high-voltage transistor and a level shifter connected to a gate terminal of the high-voltage transistor. The second switching circuit includes a first low-voltage transistor, a level shifter connected to a gate terminal of the first low-voltage transistor, and a diode disposed between the first low-voltage transistor and the output terminal. The third switching circuit includes a second low-voltage transistor and a diode disposed between the second low-voltage transistor and the output terminal.
摘要翻译：提供了一种电压选择电路，用于输出从多个输入电位中选择的电位，该电压选择电路能够选择性地输出最高电位的第一高电平电位，第二高电位电位或第三高电平电位是其输出端子的最低电位。电压选择电路包括向输出端提供第一高电平电位的第一开关电路，向输出端提供第二高电位电位的第二开关电路和供给第三高电位电位的第三开关电路，电平电位到输出端子。第一开关电路包括高压晶体管和连接到高电压晶体管的栅极端子的电平移位器。第二开关电路包括第一低压晶体管，连接到第一低压晶体管的栅极端子的电平移位器和设置在第一低压晶体管和输出端子之间的二极管。第三开关电路包括第二低压晶体管和设置在第二低压晶体管和输出端之间的二极管。

6. 发明授权

US07739560B2 Nonvolatile semiconductor memory device and method of self-testing the same 有权
标题翻译：非易失性半导体存储器件及其自检方法相同
公开(公告)号：US07739560B2
公开(公告)日：2010-06-15
申请号：US11567995
申请日：2006-12-07
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C29/00
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/3459 , G11C29/16 , G11C29/44 , G11C29/48 , G11C29/765 , G11C2029/0409 , G11C2029/1208 , G11C2229/723
摘要： A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and selects the test information stored in the test storage circuit. The sense amplifier reads out, from the test storage circuit, the test information selected by the decoder. The holding circuit holds the test information read out by the sense amplifier. The control circuit controls a test operation of checking whether the memory cell normally operates, on the basis of the test information held in the holding circuit. The defect storage circuit is formed for the memory cell, and stores fail information indicating that the memory cell is defective if the memory cell does not normally operate in the test operation.
摘要翻译：测试接口接收指定执行存储器单元的测试的测试命令。测试存储电路存储执行测试所需的测试信息。测试存储电路包括可擦除可编程存储单元。解码器对测试接口的测试命令输入进行解码，并选择存储在测试存储电路中的测试信息。读出放大器从测试存储电路读出由解码器选择的测试信息。保持电路保持由读出放大器读出的测试信息。控制电路基于保持在保持电路中的测试信息来控制检查存储单元是否正常工作的测试操作。为存储单元形成缺陷存储电路，并且如果在测试操作中存储单元不正常地操作，则存储指示存储单元有故障的故障信息。

7. 发明申请

US20070165454A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF SELF-TESTING THE SAME 有权
标题翻译：非易失性半导体存储器件及其自身测试方法
公开(公告)号：US20070165454A1
公开(公告)日：2007-07-19
申请号：US11567995
申请日：2006-12-07
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/04 , G11C16/3459 , G11C29/16 , G11C29/44 , G11C29/48 , G11C29/765 , G11C2029/0409 , G11C2029/1208 , G11C2229/723
摘要： A test interface receives a test command designating execution of a test for a memory cell. The test storage circuit stores test information necessary to execute the test. The test storage circuit includes an erasable programmable storage unit. The decoder decodes the test command input to the test interface, and selects the test information stored in the test storage circuit. The sense amplifier reads out, from the test storage circuit, the test information selected by the decoder. The holding circuit holds the test information read out by the sense amplifier. The control circuit controls a test operation of checking whether the memory cell normally operates, on the basis of the test information held in the holding circuit. The defect storage circuit is formed for the memory cell, and stores fail information indicating that the memory cell is defective if the memory cell does not normally operate in the test operation.
摘要翻译：测试接口接收指定执行存储器单元的测试的测试命令。测试存储电路存储执行测试所需的测试信息。测试存储电路包括可擦除可编程存储单元。解码器对测试接口的测试命令输入进行解码，并选择存储在测试存储电路中的测试信息。读出放大器从测试存储电路读出由解码器选择的测试信息。保持电路保持由读出放大器读出的测试信息。控制电路基于保持在保持电路中的测试信息来控制检查存储单元是否正常工作的测试操作。为存储单元形成缺陷存储电路，并且如果在测试操作中存储单元不正常地操作，则存储指示存储单元有故障的故障信息。

8. 发明申请

US20070133290A1 SEMICONDUCTOR MEMORY DEVICE EQUIPPED WITH STORAGE SECTION FOR STORING SETTING INFORMATION TO SET INITIAL OPERATION AND FUNCTION 有权
标题翻译：装有存储部分的半导体存储器件存储设置信息以设置初始操作和功能
公开(公告)号：US20070133290A1
公开(公告)日：2007-06-14
申请号：US11609476
申请日：2006-12-12
申请人： Hidetoshi Saito
发明人： Hidetoshi Saito
IPC分类号： G11C16/04 , G11C8/00
CPC分类号： G11C16/10 , G11C16/3436
摘要： A device includes first and second memory cell arrays, first and second decoders, first and second sense amplifiers, and first and second switch circuits. The first switch circuit switches the supply of writing and erasing voltages or a reading voltage to the first memory cell array, and switches the supply of writing and erasing addresses or a reading address to the first decoder, and switches the connection of a data line connected to the first memory cell array to the first sense amplifier. The second switch circuit switches the supply of writing and easing voltages or a reading voltage to one of the second memory cell arrays, and switches the supply of writing and erasing addresses or a reading address to one of the second decoders, and switches the connection of a data line connected to the second memory cell arrays to the second sense amplifier.
摘要翻译：一种器件包括第一和第二存储单元阵列，第一和第二解码器，第一和第二读出放大器以及第一和第二开关电路。第一开关电路将写入和擦除电压的供给或读取电压切换到第一存储单元阵列，并将写入和擦除地址的供应或读取地址切换到第一解码器，并切换连接的数据线的连接到第一读出放大器的第一存储单元阵列。第二开关电路将写入和放宽电压的供给或读取电压切换到第二存储单元阵列之一，并将写入和擦除地址的供给或读取地址切换到第二解码器之一，并且切换连接到第二存储单元阵列到第二读出放大器的数据线。

9. 发明授权

US07126855B2 Semiconductor device that enables simultaneous read and write/read operation 失效
标题翻译：实现同时读/写操作的半导体器件
公开(公告)号：US07126855B2
公开(公告)日：2006-10-24
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.
摘要翻译：半导体器件具有存储单元阵列，其具有多个核心的布置，每个核心包括一个块或一组多个块，每个块定义作为数据擦除单位的存储单元的范围。半导体器件具有存储体设置存储器电路，其被配置为选择核心的可选数量的核心作为第一存储体，并且将剩余的核心设置为第二存储体，以便允许数据读取操作以在第一和第二组中的另一个中进行数据写入或擦除操作的第一和第二存储体。

10. 发明申请

US20050207247A1 Semiconductor device that enables simultaneous read and write/read operation 失效
公开(公告)号：US20050207247A1
公开(公告)日：2005-09-22
申请号：US11125073
申请日：2005-05-10
申请人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
发明人： Yasuhiko Honda , Hideo Kato , Hidetoshi Saito , Masao Kuriyama , Tokumasa Hara , Takafumi Ikeda , Tatsuya Hiramatsu
IPC分类号： G11C16/00 , G11C5/00 , G11C8/12 , G11C16/10 , G11C16/26
CPC分类号： G11C8/12 , G11C16/10 , G11C16/26 , G11C2216/22
摘要： A semiconductor device has a memory cell array having the arrangement of a plurality of cores, each of which comprises one block or a set of a plurality of blocks, each block defining a range of memory cells serving as a unit of data erase. The semiconductor device has a bank setting memory circuit configured to select an optional number of cores of the cores as a first bank and to set the remaining cores as a second bank, so as to allow a data read operation to be carried out in one of the first and second banks while a data write or erase operation is carried out in the other of the first and second banks.

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