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1. 发明授权

US4455495A Programmable semiconductor integrated circuitry including a programming semiconductor element 失效
标题翻译：包括编程半导体元件的可编程半导体集成电路
公开(公告)号：US4455495A
公开(公告)日：1984-06-19
申请号：US192869
申请日：1980-10-01
申请人： Toshiaki Masuhara , Osamu Minato , Katsuhiro Shimohigashi , Hiroo Masuda , Hideo Sunami , Yoshio Sakai , Yoshiaki Kamigaki , Eiji Takeda , Yoshimune Hagiwara
发明人： Toshiaki Masuhara , Osamu Minato , Katsuhiro Shimohigashi , Hiroo Masuda , Hideo Sunami , Yoshio Sakai , Yoshiaki Kamigaki , Eiji Takeda , Yoshimune Hagiwara
IPC分类号： G11C8/10 , G11C17/16 , G11C17/18 , G11C29/00 , H01L21/263 , H01L21/268 , H01L21/768 , H01L23/525 , H01L27/10 , H01L27/04 , H01L29/04
CPC分类号： G11C29/785 , G11C17/16 , G11C17/18 , G11C8/10 , H01L21/2636 , H01L21/268 , H01L21/76894 , H01L23/5254 , H01L27/10 , H01L2924/0002
摘要： A programmable semiconductor integrated circuitry including a circuit programming element is disclosed. The circuit programming element can be activated in a short-circuit mode by the irradiation of a laser or electron beam or by ion implantation so that it is converted from its original nonconductive state into a conductive or conductable state, thereby providing electrical connection between circuits and/or circuit elements of the integrated circuitry for a desired circuit programming such as circuit creation, circuit conversion or circuit substitution.
摘要翻译：公开了一种包括电路编程元件的可编程半导体集成电路。电路编程元件可以通过激光或电子束的照射或通过离子注入在短路模式中被激活，使得其从其原始的非导通状态转换为导电或导电状态，由此提供电路之间的电连接 /或集成电路的电路元件，用于所需的电路编程，例如电路创建，电路转换或电路替换。

2. 发明授权

US4656492A Insulated gate field effect transistor 失效
标题翻译：绝缘栅场效应晶体管
公开(公告)号：US4656492A
公开(公告)日：1987-04-07
申请号：US786715
申请日：1985-10-15
申请人： Hideo Sunami , Hiroo Masuda , Yoshiaki Kamigaki , Katsuhiro Shimohigashi , Eiji Takeda
发明人： Hideo Sunami , Hiroo Masuda , Yoshiaki Kamigaki , Katsuhiro Shimohigashi , Eiji Takeda
IPC分类号： H01L29/08 , H01L29/10 , H01L29/78 , H01L29/76 , H01L29/94
CPC分类号： H01L29/7838 , H01L29/0847 , H01L29/1083 , H01L29/78 , H01L29/7836
摘要： An insulated gate field effect transistor is formed in one surface of a semiconductor substrate. The surface portion of a channel has an impurity distribution of the conduction type opposite to that of the substrate, which the deeper portion of the channel has an impurity distribution of the same conduction type as that of the substrate. Moreover, at least one of a source and a drain is formed of such an impurity layer of the conduction type opposite to that of the substrate as has its impurity distribution gently sloped by double diffusion processes.
摘要翻译：绝缘栅场效应晶体管形成在半导体衬底的一个表面中。通道的表面部分具有与衬底相反的导电类型的杂质分布，其中沟道的较深部分具有与衬底相同导电类型的杂质分布。此外，源极和漏极中的至少一个由具有与衬底相反的导电类型的杂质层形成，其杂质分布通过双扩散过程缓缓倾斜。

3. 发明授权

US4041521A Shift array for pattern information processing device utilizing charge coupled semiconductor device 失效
标题翻译：利用电荷耦合半导体器件的图形信息处理装置的移位阵列
公开(公告)号：US4041521A
公开(公告)日：1977-08-09
申请号：US298569
申请日：1972-10-18
申请人： Hideo Sunami , Yokichi Itoh , Fumiyuki Inose , Yoshiaki Kamigaki
发明人： Hideo Sunami , Yokichi Itoh , Fumiyuki Inose , Yoshiaki Kamigaki
IPC分类号： G11C27/04 , H01L21/339 , H01L27/105 , H01L29/423 , H01L29/762 , H01L29/78
CPC分类号： H01L27/1057 , H01L29/42396
摘要： A shift array for shifting carriers introduced into a semiconductor body toward the X-direction and Y-direction comprises an insulating layer disposed on the semiconductor body, first electrodes disposed on the insulating layer and arranged in a matrix on the X-Y plane, second electrodes disposed between adjacent first electrodes, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each row when carriers are transferred toward the Y-direction, conductors disposed adjacent to the first electrodes to be connected to the electrodes of each column when carriers are transferred toward the X-direction. When carriers are transferred toward the X-direction, the second electrodes disposed between the adjacent first electrodes of each column are biased with a DC voltage whose electrical polarity is reversed relative to the DC voltage applied to the first electrodes for preventing the transit of carriers toward the Y-direction. When carriers are transferred toward the Y-direction, the second electrodes disposed between the adjacent first electrodes of each row are biased with a DC voltage whose polarity is reversed relative to the DC voltage applied to the first electrodes for preventing the transit of carriers toward the X-direction.
摘要翻译：用于将引入半导体本体的载流子移动到X方向和Y方向的移位阵列包括设置在半导体本体上的绝缘层，设置在绝缘层上并以矩阵形式布置在XY平面上的第一电极，第二电极设置在相邻的第一电极之间，当载体朝着Y方向转移时，邻近第一电极设置的导体设置成与每行的电极连接，当载体为载体时，与第一电极邻近设置的导体连接到每列的电极向X方向转移。当载体向X方向转移时，设置在每列的相邻第一电极之间的第二电极被以直流电压偏置，该DC电压的电极性相对于施加到第一电极的DC电压反转，以防止载流子朝向 Y方向。当载体朝向Y方向转移时，设置在每行的相邻第一电极之间的第二电极被以直流电压偏置，该直流电压的极性相对于施加到第一电极的直流电压而相反，以防止载流子朝向 X方向。

4. 发明授权

US4013897A Information signal transfer method and a charge transfer 失效
标题翻译：信息信号传输方法和电荷传输
公开(公告)号：US4013897A
公开(公告)日：1977-03-22
申请号：US520095
申请日：1974-11-01
申请人： Yoshiaki Kamigaki , Hideo Sunami , Yokichi Itoh
发明人： Yoshiaki Kamigaki , Hideo Sunami , Yokichi Itoh
IPC分类号： G11C19/28 , H01L29/768 , H01L29/78
CPC分类号： G11C19/285 , H01L29/76808
摘要： A charge transfer device and method are disclosed in which a plurality of signal charges corresponding to one information input signal are injected into a surface region of a semiconductor substrate beneath specific ones of a plurality of transfer gate electrodes corresponding to said signal charges and transferred therethrough by the transfer gate electrodes. Transferred signal charges subsequent to the first signal charge transferred are detected, thereby using residual charges to prevent decrease in the amount of the detected transfer charges and thus allowing the output signal to appear at the output terminal with a minimum of attenuation even if an increased number of transfer gate electrodes are used.

5. 发明申请

US20060220100A1 Semicondudctor device 有权
标题翻译：半导体器件
公开(公告)号：US20060220100A1
公开(公告)日：2006-10-05
申请号：US11415129
申请日：2006-05-02
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： H01L29/788
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

6. 发明申请

US20050258474A1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US20050258474A1
公开(公告)日：2005-11-24
申请号：US10484578
申请日：2002-07-22
申请人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
发明人： Toshihiro Tanaka , Yukiko Umemoto , Mitsuru Hiraki , Yutaka Shinagawa , Masamichi Fujito , Kazufumi Suzukawa , Hiroyuki Tanikawa , Takashi Yamaki , Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Nozomu Matsuzaki
IPC分类号： G11C16/04 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/105 , H01L29/423 , H01L29/78 , H01L29/788 , H01L29/792
CPC分类号： G11C16/26 , G11C5/025 , G11C8/08 , G11C16/04 , G11C16/0425 , G11C16/0433 , G11C16/08 , G11C16/24 , G11C16/30 , H01L21/28 , H01L21/28273 , H01L27/105 , H01L27/115 , H01L27/11521 , H01L27/11526 , H01L27/11546 , H01L29/42328 , H01L29/42332 , H01L29/4234 , H01L29/66825 , H01L29/7885 , H01L29/792
摘要： A semiconductor device includes a plurality of nonvolatile memory cells (1). Each of the nonvolatile memory cells comprises a MOS type first transistor section (3) used for information storage, and a MOS type second transistor section (4) which selects the first transistor section. The second transistor section has a bit line electrode (16) connected to a bit line, and a control gate electrode (18) connected to a control gate control line. The first transistor section has a source line electrode (10) connected to a source line, a memory gate electrode (14) connected to a memory gate control line, and a charge storage region (11) disposed directly below the memory gate electrode. A gate withstand voltage of the second transistor section is lower than that of the first transistor section. Assuming that the thickness of a gate insulating film of the second transistor section is defined as tc and the thickness of a gate insulating film of the first transistor section is defined as tm, they have a relationship of tc
摘要翻译：半导体器件包括多个非易失性存储单元（1）。每个非易失性存储单元包括用于信息存储的MOS型第一晶体管部分（3）和选择第一晶体管部分的MOS型第二晶体管部分（4）。第二晶体管部分具有连接到位线的位线电极（16）和连接到控制栅极控制线的控制栅电极（18）。第一晶体管部分具有连接到源极线的源极线电极（10），连接到存储器栅极控制线的存储栅电极（14）和直接位于存储栅电极下方的电荷存储区域（11）。第二晶体管部分的栅极耐受电压低于第一晶体管部分的栅极耐受电压。假设第二晶体管部分的栅极绝缘膜的厚度被定义为tc，并且第一晶体管部分的栅极绝缘膜的厚度被定义为tm，它们具有tc

7. 发明授权

US06590809B2 Non-volatile semiconductor memory device 有权
公开(公告)号：US06590809B2
公开(公告)日：2003-07-08
申请号：US10040332
申请日：2002-01-09
申请人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
发明人： Takanori Yamazoe , Hiroshi Yoshigi , Yoshiaki Kamigaki , Kozo Katayama , Shinichi Minami , Takeo Kanai
IPC分类号： G11C1604
CPC分类号： G11C16/0433 , G11C11/5671 , G11C16/0475 , G11C16/10 , G11C16/26
摘要： When two bits are stored per memory cell and the two bits are written or read, writing or reading operation has to be performed twice. When a memory array is constructed by using a memory cell, by the access of twice, read time or write time twice as long as conventional read or write time is required. It causes deterioration in speed of a system using the memory. To solve the problem, according to the invention, bit arrangement of a conventional memory cell array is changed according to a writing or reading method With the configuration, a plurality of bytes can be simultaneously written or read by a single access. In order to perform reading at higher speed, a sense amplifier requiring no precharging is also provided.

8. 发明授权

US06531735B1 Semiconductor integrated circuit 失效
标题翻译：半导体集成电路
公开(公告)号：US06531735B1
公开(公告)日：2003-03-11
申请号：US09660923
申请日：2000-09-13
申请人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
发明人： Yoshiaki Kamigaki , Shinichi Minami , Kozo Katayama , Masataka Kato
IPC分类号： H01L29792
CPC分类号： H01L27/11568 , G11C11/5671 , G11C16/0475 , H01L21/28273 , H01L21/28282 , H01L27/0207 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A multi-storage nonvolatile memory of high density, high speed and high reliability has a memory transistor and switch transistors disposed on both the sides of the memory transistor. The memory transistor includes a gate insulating film having discrete traps and a memory gate electrode, whereas the switch transistors include switch gate electrodes. The gate insulating film has the discrete traps for storing information charge, can locally inject carriers, and one memory cell constitutes a multi-storage cell for storing at least information of 2 bits. The switch transistors having the switch gate electrodes realize source side injection. The memory transistor is fommed together with the switch transistors in self-aligned diffusion. The memory gate electrode of the memory transistor is connected to a word line so as to perform word-line erase.
摘要翻译：高密度，高速度和高可靠性的多存储非易失性存储器具有置于存储晶体管的两侧的存储晶体管和开关晶体管。存储晶体管包括具有离散陷阱和存储栅电极的栅极绝缘膜，而开关晶体管包括开关栅电极。栅极绝缘膜具有用于存储信息电荷的离散陷阱，可以局部注入载流子，并且一个存储器单元构成用于至少存储2位信息的多存储单元。具有开关栅电极的开关晶体管实现源极侧注入。存储晶体管与自对准扩散中的开关晶体管一起发生。存储晶体管的存储栅电极连接到字线，以便执行字线擦除。

9. 发明授权

US4769787A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4769787A
公开(公告)日：1988-09-06
申请号：US888072
申请日：1986-07-22
申请人： Kazunori Furusawa , Shinji Nabetani , Yoshiaki Kamigaki , Masaaki Terasawa
发明人： Kazunori Furusawa , Shinji Nabetani , Yoshiaki Kamigaki , Masaaki Terasawa
IPC分类号： G11C16/04 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/14 , G11C17/00 , G11C11/34
CPC分类号： G11C16/08 , G11C16/0466 , G11C16/10 , G11C16/12 , G11C16/14
摘要： Using a comparatively low supply voltage of, e.g., +5V and a minus gate voltage, the voltage difference between the gate of an MNOS transistor and a P-type well region in which a MNOS transistor is formed is relatively changed to execute the writing and erasing of the MNOS transistor. Thus, the potential of an N-type semiconductor substrate can be fixed to a comparatively low potential, e.g., about +5V, so that a P-channel MOSFET formed on the semiconductor substrate operates with an ordinary signal level. Consequently, an EEPROM having peripheral circuits constructed of CMOS circuits can be provided. Accordingly, reduction in the power consumption of the EEPROM can be attained.
摘要翻译：使用例如+ 5V和负栅极电压的较低电源电压，MNOS晶体管的栅极与其中形成MNOS晶体管的P型阱区域之间的电压差相对变化，以执行写入和擦除MNOS晶体管。因此，N型半导体衬底的电位可以固定在比较低的电位，例如约+ 5V，使得形成在半导体衬底上的P沟道MOSFET以普通信号电平工作。因此，可以提供具有由CMOS电路构成的外围电路的EEPROM。因此，可以实现EEPROM的功耗的降低。

10. 发明授权

US07064090B2 Method of manufacturing a semiconductor integrated circuit device 失效
标题翻译：制造半导体集成电路器件的方法
公开(公告)号：US07064090B2
公开(公告)日：2006-06-20
申请号：US10942860
申请日：2004-09-17
申请人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
发明人： Shinichi Minami , Yoshiaki Kamigaki , Hideki Yasuoka , Fukuo Owada
IPC分类号： H01L21/00
CPC分类号： H01L27/11526 , H01L27/0629 , H01L27/105 , H01L27/1052 , H01L27/11521 , H01L27/11546 , Y10S438/983
摘要： A manufacturing technique for a zener diode which includes forming a first semiconductor region in a region such as a well region at a primary face of a semiconductor substrate and then forming a second semiconductor region of opposite conductivity type thereover. The second semiconductor region covers an area greater than the underlying first semiconductor region. The method further calls for forming an insulating film on the primary face of the substrate followed by the forming connection holes in the insulating film to expose an upper part of the second semiconductor region located outside the area covered by the junction affected between the first and second semiconductor regions. This is followed by the formation of a wire at the upper part of the insulating film in which an electrical connection is affected between the wire and the second semiconductor region through the plural connection holes which are distributively arranged.
摘要翻译：一种用于齐纳二极管的制造技术，其包括在半导体衬底的初级面的诸如阱区域的区域中形成第一半导体区域，然后在其上形成相反导电类型的第二半导体区域。第二半导体区域覆盖大于下面的第一半导体区域的面积。该方法还要求在衬底的主面上形成绝缘膜，然后在绝缘膜中形成连接孔，以暴露第二半导体区域的上部，该第二半导体区域的上部位于由第一和第二半导体区域。接着在绝缘膜的上部形成通过分布布置的多个连接孔在电线和第二半导体区域之间形成电连接的导线。

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