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1. 发明授权

US08909689B2 Arithmetic device 有权
标题翻译：算术设备
公开(公告)号：US08909689B2
公开(公告)日：2014-12-09
申请号：US13361074
申请日：2012-01-30
申请人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
发明人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
IPC分类号： G06F7/72
CPC分类号： G06F7/728
摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
摘要翻译：根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果量。当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

2. 发明申请

US20120131078A1 ARITHMETIC DEVICE 有权
标题翻译：算术设备
公开(公告)号：US20120131078A1
公开(公告)日：2012-05-24
申请号：US13361074
申请日：2012-01-30
申请人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
发明人： Hideo Shimizu , Yuichi Komano , Koichi Fujisaki , Shinichi Kawamura
IPC分类号： G06F7/523 , G06F7/50 , G06F5/01 , G06F7/48
CPC分类号： G06F7/728
摘要： According to one embodiment, a first shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of an intermediate result of a computation of Montgomery multiplication result z and calculates a first shift amount. A second shift amount calculation unit counts the number of continuous zeros from a less significant bit toward a more significant bit of redundant-binary-represented integer x and calculates a second shift amount. An addition/subtraction unit calculates the intermediate result by adding/subtracting, with respect to the intermediate result which has been bit-shifted by the first shift amount, the integer p, and the integer y which has been bit-shifted by the second shift amount. An output unit outputs, as the Montgomery multiplication result z, the intermediate result when the sum of the first shift amounts is equal to the number of bits of the integer p.
摘要翻译：根据一个实施例，第一移位量计算单元从蒙哥马利乘积结果z的计算的中间结果的较低有效位向更高有效位对连续零的数进行计数，并计算第一移位量。第二移位量计算单元将来自冗余二进制表示的整数x的较低有效位朝向更高有效位的连续零的数目计数，并计算第二移位量。加法/减法单元相对于已被移位了第一移位量的中间结果，整数p和已被位移第二移位的整数y加/减来计算中间结果量。当第一移位量的和等于整数p的位数时，输出单元输出作为蒙哥马利乘数结果z的中间结果。

3. 发明申请

US20120307997A1 ENCRYPTION DEVICE 有权
标题翻译：加密设备
公开(公告)号：US20120307997A1
公开(公告)日：2012-12-06
申请号：US13585391
申请日：2012-08-14
申请人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/28
CPC分类号： H04L9/0631 , H04L9/003
摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.
摘要翻译：根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

4. 发明授权

US09288040B2 Encryption device 有权
标题翻译：加密设备
公开(公告)号：US09288040B2
公开(公告)日：2016-03-15
申请号：US13585391
申请日：2012-08-14
申请人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
发明人： Tsukasa Endo , Yuichi Komano , Koichi Fujisaki , Hideo Shimizu , Hanae Ikeda , Atsushi Shimbo
IPC分类号： H04L9/06 , H04L9/00
CPC分类号： H04L9/0631 , H04L9/003
摘要： According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.
摘要翻译：根据实施例，加密装置使用加密密钥进行加密处理，并从普通数据计算加密数据。加密装置包括：寄存器; 输入单元，被配置为接收普通数据; 第一部分加密单元，被配置为从所述普通数据计算第一中间数据; 第二部分加密单元，被配置为基于第i个中间数据和加密密钥计算第（i + 1）个中间数据; 第一变换单元，被配置为：将第j个中间数据变换为第j变换数据; 并将第j个变换数据存储在寄存器中; 以及第二变换单元，被配置为将第j个变换后的数据变换为第j个中间数据; 第三部分加密单元，被配置为从第N个中间数据计算加密数据。第二部分加密单元被配置为重复处理以计算（j + 1）中间数据，而j等于从1到N-1。

5. 发明授权

US08401180B2 Non-linear data converter, encoder and decoder 有权
标题翻译：非线性数据转换器，编码器和解码器
公开(公告)号：US08401180B2
公开(公告)日：2013-03-19
申请号：US12053143
申请日：2008-03-21
申请人： Yuichi Komano , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
发明人： Yuichi Komano , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
IPC分类号： H04K1/00
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译：根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

6. 发明申请

US20080292100A1 NON-LINEAR DATA CONVERTER, ENCODER AND DECODER 有权
标题翻译：非线性数据转换器，编码器和解码器
公开(公告)号：US20080292100A1
公开(公告)日：2008-11-27
申请号：US12053143
申请日：2008-03-21
申请人： Yuichi KOMANO , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
发明人： Yuichi KOMANO , Hideo Shimizu , Koichi Fujisaki , Hideyuki Miyake , Atsushi Shimbo
IPC分类号： H04L9/06
CPC分类号： H04L9/0618 , H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/24
摘要： According to an aspect of the present invention, there is provided a non-linear data converter including: first to fourth converters that each performs a respective converting process on an input bit string to output respective output bit string; a generator that generates a random number bit string; and a selector that selects any one of the output bit strings from the first to fourth converters based on the random number bit string. Each of the converting processes is equivalent to performing a first mask process, a non-linear conversion predetermined for an encoding or a decoding and a second mask process.
摘要翻译：根据本发明的一个方面，提供了一种非线性数据转换器，包括：第一至第四转换器，其对输入的比特串执行相应的转换处理，以输出相应的输出比特串; 产生随机数位串的发生器; 以及选择器，其基于随机数位串来选择来自第一至第四转换器的输出位串中的任何一个。每个转换处理等效于执行第一掩码处理，为编码或解码预定的非线性转换和第二掩码处理。

7. 发明申请

US20070005895A1 Cache memory device and microprocessor 失效
标题翻译：高速缓存存储器和微处理器
公开(公告)号：US20070005895A1
公开(公告)日：2007-01-04
申请号：US11477398
申请日：2006-06-30
申请人： Koichi Fujisaki , Hideo Shimizu
发明人： Koichi Fujisaki , Hideo Shimizu
IPC分类号： G06F12/00
CPC分类号： G06F12/0802 , G06F12/0886 , G06F12/14 , G06F2212/601
摘要： A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache memory is provided with a plurality of cache lines that include a tag area storing an address on the main memory, a capacity area storing a capacity value of a cache block, and a cache block. When a read request is executed from the processor to the main memory, the cache controller checks whether the requested data is present in the cache memory or not. A cache capacity determination unit determines a capacity value for the cache block and supplies to a capacity area.
摘要翻译：缓存控制器连接到处理器和主存储器。高速缓存控制器还连接到可以以比主存储器高的速度读写的高速缓冲存储器。高速缓冲存储器设置有多条高速缓存线，其包括存储主存储器上的地址的标签区域，存储高速缓存块的容量值的容量区域和高速缓存块。当从处理器向主存储器执行读请求时，高速缓存控制器检查所请求的数据是否存在于高速缓冲存储器中。高速缓存容量确定单元确定高速缓存块的容量值并提供给容量区。

8. 发明授权

US08023643B2 Encryption/decryption apparatus 有权
标题翻译：加密/解密装置
公开(公告)号：US08023643B2
公开(公告)日：2011-09-20
申请号：US11511401
申请日：2006-08-29
申请人： Koichi Fujisaki , Hideo Shimizu , Atsushi Shimbo
发明人： Koichi Fujisaki , Hideo Shimizu , Atsushi Shimbo
IPC分类号： H04L9/22
CPC分类号： H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/12
摘要： A first Exclusive OR circuit operates an Exclusive OR between input data and a predetermined random number. An operation circuit performs one operation of encryption and decryption of output data from the first Exclusive OR circuit. A data register circuit, which has a plurality of data hold units, holds data from the operation circuit in one data hold unit of the plurality of data hold units in response to a selection signal, and supplies the data from the one data hold unit to the operation circuit. A second Exclusive OR circuit performs an Exclusive OR between output data from the data register circuit and the random number. The operation circuit recursively performs the one operation of the data from the data register circuit and outputs next data to the data register circuit.
摘要翻译：第一异或电路在输入数据和预定的随机数之间操作异或。操作电路对来自第一异或电路的输出数据进行加密和解密的一个操作。具有多个数据保持单元的数据寄存器电路响应于选择信号在多个数据保持单元的一个数据保持单元中保存来自运算电路的数据，并将来自一个数据保持单元的数据提供给操作电路。第二个异或电路在数据寄存器电路的输出数据和随机数之间执行异或运算。运算电路从数据寄存器电路递归地执行数据的一次操作，并将下一个数据输出到数据寄存器电路。

9. 发明申请

US20070071235A1 Encryption/decryption appararus 有权
标题翻译：加密/解密appararus
公开(公告)号：US20070071235A1
公开(公告)日：2007-03-29
申请号：US11511401
申请日：2006-08-29
申请人： Koichi Fujisaki , Hideo Shimizu , Atsushi Shimbo
发明人： Koichi Fujisaki , Hideo Shimizu , Atsushi Shimbo
IPC分类号： H04L9/28
CPC分类号： H04L9/003 , H04L2209/046 , H04L2209/08 , H04L2209/12
摘要： A first Exclusive OR circuit operates an Exclusive OR between input data and a predetermined random number. An operation circuit performs one operation of encryption and decryption of output data from the first Exclusive OR circuit. A data register circuit, which has a plurality of data hold units, holds data from the operation circuit in one data hold unit of the plurality of data hold units in response to a selection signal, and supplies the data from the one data hold unit to the operation circuit. A second Exclusive OR circuit performs an Exclusive OR between output data from the data register circuit and the random number. The operation circuit recursively performs the one operation of the data from the data register circuit and outputs next data to the data register circuit.
摘要翻译：第一异或电路在输入数据和预定的随机数之间操作异或。操作电路对来自第一异或电路的输出数据进行加密和解密的一个操作。具有多个数据保持单元的数据寄存器电路响应于选择信号在多个数据保持单元的一个数据保持单元中保存来自运算电路的数据，并将来自一个数据保持单元的数据提供给操作电路。第二个异或电路在数据寄存器电路的输出数据和随机数之间执行异或运算。运算电路从数据寄存器电路递归地执行数据的一次操作，并将下一个数据输出到数据寄存器电路。

10. 发明授权

US07480777B2 Cache memory device and microprocessor 失效
标题翻译：高速缓存存储器和微处理器
公开(公告)号：US07480777B2
公开(公告)日：2009-01-20
申请号：US11477398
申请日：2006-06-30
申请人： Koichi Fujisaki , Hideo Shimizu
发明人： Koichi Fujisaki , Hideo Shimizu
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0802 , G06F12/0886 , G06F12/14 , G06F2212/601
摘要： A cache controller is connected to a processor and a main memory. The cache controller is also connected to a cache memory that can read and write at a speed higher than the main memory. The cache memory is provided with a plurality of cache lines that include a tag area storing an address on the main memory, a capacity area storing a capacity value of a cache block, and a cache block. When a read request is executed from the processor to the main memory, the cache controller checks whether the requested data is present in the cache memory or not. A cache capacity determination unit determines a capacity value for the cache block and supplies to a capacity area.
摘要翻译：缓存控制器连接到处理器和主存储器。高速缓存控制器还连接到可以以比主存储器高的速度读写的高速缓冲存储器。高速缓冲存储器设置有多条高速缓存线，其包括存储主存储器上的地址的标签区域，存储高速缓存块的容量值的容量区域和高速缓存块。当从处理器向主存储器执行读请求时，高速缓存控制器检查所请求的数据是否存在于高速缓冲存储器中。高速缓存容量确定单元确定高速缓存块的容量值并提供给容量区。

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