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1. 发明授权

US07978543B2 Semiconductor device testable on quality of multiple memory cells in parallel and testing method of the same 有权
标题翻译：半导体器件可以测试多个存储单元的质量并行测试方法
公开(公告)号：US07978543B2
公开(公告)日：2011-07-12
申请号：US12488920
申请日：2009-06-22
申请人： Hideo Inaba , Tadashi Onodera
发明人： Hideo Inaba , Tadashi Onodera
IPC分类号： G11C7/10
CPC分类号： G11C29/48 , G11C29/1201
摘要： A semiconductor device includes: first and second input/output terminals; a first input/output line connected to the first input/output terminal; a second input/output line connected to the second input/output terminal; and a first by-path route that connects the first input/output line and the second input/output line. When in normal operation mode, the first by-path route is set in a non-conductive state. When in a test mode, the first by-path route is set into a conductive state so that a first data inputted to the first input/output terminal is outputted as a first data to the second input/output line, in correspondence with a transition of a clock signal in the first direction, and so that a second data inputted to said first input/output terminal is outputted as a second input data for said first input/output line, in correspondence with a transition of said clock signal in the second direction.
摘要翻译：半导体器件包括：第一和第二输入/输出端子; 连接到第一输入/输出端的第一输入/输出线; 连接到第二输入/输出端子的第二输入/输出线; 以及连接第一输入/输出线和第二输入/输出线的第一旁路路径。当处于正常操作模式时，第一个旁路路由被设置为非导通状态。当处于测试模式时，将第一旁路路径设置为导通状态，使得输入到第一输入/输出端的第一数据作为第一数据输出到第二输入/输出线，并且使得输入到所述第一输入/输出端的第二数据作为所述第一输入/输出线的第二输入数据被输出，以对应于所述第二输入/输出端中的所述时钟信号的转变方向。

2. 发明授权

US07054224B2 Non-synchronous semiconductor memory device having page mode read/write 有权
标题翻译：具有页模式读/写的非同步半导体存储器件
公开(公告)号：US07054224B2
公开(公告)日：2006-05-30
申请号：US10478369
申请日：2002-05-23
申请人： Hiroyuki Takahashi , Hideo Inaba , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Hideo Inaba , Atsushi Nakagawa
IPC分类号： G11C8/00
CPC分类号： G11C11/40615 , G11C7/1012 , G11C7/1051 , G11C11/406 , G11C11/4096
摘要： The present invention provides a non-synchronous semiconductor memory device configured as a pseudo-SRAM and capable of relaxing the limitation to address skew and improving the read rate. A data latch circuit 110 holds data having been read out of memory cells in a memory cell array 106 designated by a tow address included in an address ADD in a read mode. Upon transitions of column addresses A0, A1 included in the address, a multiplexer 111 sequentially and non-synchronously feeds out the data held in the data latch circuit 110 based on the column addresses A0, A1.
摘要翻译：本发明提供一种被配置为伪SRAM的非同步半导体存储器件，并且能够放宽对寻址偏移的限制并提高读取速率。数据锁存电路110将从存储单元读出的数据保存在由读取模式中包含在地址ADD中的拖尾地址指定的存储单元阵列106中。在地址中包括的列地址A 0，A 1的转换中，多路复用器111基于列地址A 0，A 1顺序地并且不同步地馈送保存在数据锁存电路110中的数据。

3. 发明申请

US20050207252A1 Semiconductor storage device, test method therefor, and test circuit therefor 失效
标题翻译：半导体存储装置及其测试方法及其测试电路
公开(公告)号：US20050207252A1
公开(公告)日：2005-09-22
申请号：US10498398
申请日：2002-12-10
申请人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
发明人： Hiroyuki Takahashi , Hideo Inaba , Syouzou Uchida
IPC分类号： G01R31/28 , G01R31/3185 , G11C8/18 , G11C11/401 , G11C11/403 , G11C11/406 , G11C29/08 , G11C29/14 , G11C7/00
CPC分类号： G11C29/12015 , G11C8/18 , G11C11/401 , G11C11/406 , G11C29/14
摘要： A test method and a test circuit which enable operations to be checked when the time interval between a refresh operation and a read or write operation is forcibly reduced. Timings for a read or write operation in a normal operation mode and in a test mode are determined on the basis of an address transition detection circuit. A timing for a refresh operation in the normal operation mode is set on the basis of a normal refreshing pulse signal generated by a refresh pulse generating circuit in response to a timing signal generated by a timer circuit. A timing for a refresh operation in the test mode is set on the basis of a first testing refresh pulse generation signal generated by a first testing refresh pulse generating circuit in response to the address transition detection signal. By controlling a timing for generating the first testing refresh pulse generation signal, it is possible to generate a read or write operation and a refresh operation so that there is a predetermined time interval between these operations.
摘要翻译：当刷新操作和读/写操作之间的时间间隔被强制降低时，能够检查操作的测试方法和测试电路。基于地址转换检测电路来确定在正常操作模式和测试模式下进行读或写操作的时序。基于由定时器电路产生的定时信号由刷新脉冲发生电路产生的正常刷新脉冲信号来设定正常操作模式下的刷新操作的定时。基于由第一测试刷新脉冲发生电路响应于地址转换检测信号产生的第一测试刷新脉冲产生信号来设置测试模式下的刷新操作的定时。通过控制用于产生第一测试刷新脉冲产生信号的定时，可以产生读或写操作和刷新操作，使得在这些操作之间存在预定的时间间隔。

4. 发明申请

US20050207214A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20050207214A1
公开(公告)日：2005-09-22
申请号：US11130464
申请日：2005-05-16
申请人： Hiroyuki Takahashi , Atsushi Nakagawa , Hideo Inaba
发明人： Hiroyuki Takahashi , Atsushi Nakagawa , Hideo Inaba
IPC分类号： G06F1/32 , G11C11/403 , G11C11/406 , G11C11/407 , G11C11/4074 , G11C11/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/4074 , G11C2207/2227 , G11C2211/4067
摘要： A semiconductor memory device is provided which effectively reduces a consumption of current of a system of circuits associated with refresh operations. A control signal circuit 2 controls n-channel transistors 3C, 4B to be in an OFF-state based on an internal chip select signal SCI in an interval time period between the refresh operations, wherein the n-channel transistors 3C, 4B are connected between the system of circuits associated with refresh operations (an internal voltage-down circuit 3 and a boost circuit 4) and the ground, so as to break down a leak path of the system of circuits associated with refresh operations for reducing the leakage of current. At a timing of starting the refresh operation by triggering a timer, the internal chip select signal SCI is transitioned to a high level for supplying a ground voltage to the internal voltage-down circuit 3 and the boost circuit 4.
摘要翻译：提供一种半导体存储器件，其有效地减少与刷新操作相关的电路系统的电流消耗。在刷新操作之间的间隔时间内，控制信号电路2基于内部片选信号SCI控制n沟道晶体管3C，4B处于截止状态，其中n沟道晶体管3 C，4 B连接在与刷新操作（内部降压电路3和升压电路4）相关联的电路系统和地之间，以便分解与刷新操作相关联的电路系统的泄漏路径，以减少电流泄漏。在通过触发定时器开始刷新操作的定时，内部芯片选择信号SCI转换到用于向内部降压电路3和升压电路4提供接地电压的高电平。

5. 发明授权

US06947345B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US06947345B2
公开(公告)日：2005-09-20
申请号：US10473656
申请日：2002-03-28
申请人： Hiroyuki Takahashi , Hideo Inaba , Atsushi Nakagawa
发明人： Hiroyuki Takahashi , Hideo Inaba , Atsushi Nakagawa
IPC分类号： G11C7/22 , G11C11/406 , G11C11/4076 , G11C7/00
CPC分类号： G11C11/40615 , G11C7/22 , G11C11/406 , G11C11/4076 , G11C2207/2227 , G11C2211/4061 , G11C2211/4067
摘要： A semiconductor memory device is provided, which is capable of effectively reducing a current comsumption caused by a self-refresh operation in a stand-by mode.In the refresh operation in the stand-by mode, under the control by a refresh control circuit 8B, firstly, a suppression is made for current driving abilities of sense amplifiers 70A˜70D provided for amplifying data signals appearing on bit lines, and secondly, an expansion is made of a pulse width of a row enable signal RE, which defines a period of time for selecting word lines WL, and thirdly, parallel activations of plural word lines are made based on the row enable signal RE with the expanded pulse width, thereby reducing the frequency of operations of the circuit system associated with the refresh operations, resulting in a suppression of the current consumption.
摘要翻译：提供一种半导体存储器件，其能够有效地降低由待机模式中的自刷新操作引起的电流消耗。在待机模式的刷新操作中，在刷新控制电路8B的控制下，首先抑制用于放大位线上出现的数据信号的读出放大器70A〜70D的电流驱动能力，其次，扩展行限制信号RE的脉冲宽度，该行允许信号RE定义了用于选择字线WL的时间段，第三，基于行允许信号RE进行多条字线的并行激活，扩大的脉冲宽度，从而降低与刷新操作相关联的电路系统的操作频率，导致电流消耗的抑制。

6. 发明授权

US06751144B2 Semiconductor storage and method for testing the same 有权
标题翻译：半导体存储和测试方法
公开(公告)号：US06751144B2
公开(公告)日：2004-06-15
申请号：US10148430
申请日：2002-05-29
申请人： Hiroyuki Takahashi , Hideo Inaba , Takashi Kusakari
发明人： Hiroyuki Takahashi , Hideo Inaba , Takashi Kusakari
IPC分类号： G11C700
CPC分类号： G11C11/40615 , G11C8/18 , G11C11/406 , G11C29/12
摘要： A semiconductor storage having the same memory cells as a DRAM, operating in SRAM specifications, and having advantages such as a small chop size, a low power consumption, a low manufacturing cost, no access delay due to skew, and no memory cell breakdown. An ATD circuit (3) generates a one-shot pulse added to an address change detection signal (ATD) from a change of the address (Address) supplied from external. By combining one-shot pulse produced for each bit of the address, only one one-shot pulse is generated even if the address includes skew. A memory cell is refreshed by using a refresh address (R_ADD) generated by a refresh control circuit (4) during the time when a one-shot pulse is generated. At the fall of the one-shot pulse, a latch control signal (LC) is generated, and the address is taken in a latch (2) so as to access a memory cell array (6).
摘要翻译：具有与DRAM相同的存储单元的半导体存储器，以SRAM规格工作，具有小斩尺寸，低功耗，低制造成本，无偏移的访问延迟以及无存储器单元故障等优点。 ATD电路（3）根据从外部提供的地址（地址）的改变产生添加到地址变化检测信号（ATD）的单触发脉冲。通过组合为地址的每个位产生的单触发脉冲，即使地址包含偏斜，也只产生一个单触发脉冲。通过使用在产生单次脉冲的时间期间由刷新控制电路（4）产生的刷新地址（R_ADD）来刷新存储器单元。在单触发脉冲的下降时，产生锁存控制信号（LC），并将该地址取入锁存器（2），以访问存储单元阵列（6）。

7. 发明授权

US06672082B1 Heat pump and dehumidifying device 失效
标题翻译：热泵和除湿装置
公开(公告)号：US06672082B1
公开(公告)日：2004-01-06
申请号：US10069119
申请日：2002-02-28
申请人： Kensaku Maeda , Hideo Inaba , Shunro Nishiwaki
发明人： Kensaku Maeda , Hideo Inaba , Shunro Nishiwaki
IPC分类号： F25D1706
CPC分类号： F25B5/04 , F24F3/1405 , F24F3/153 , F24F2012/005 , F25B40/02 , F25B41/04 , Y02B30/563
摘要： A heat pump with a high coefficient of performance and a dehumidifying apparatus consumes a small amount of energy per amount of moisture removal. The heat pump includes a pressurizer for raising a pressure of a refrigerant; a condenser for condensing the refrigerant to heat a high-temperature heat source fluid; an evaporator for evaporating the refrigerant to cool a low-temperature heat source fluid; and heat exchanger disposed in a refrigerant path connecting the condenser and the evaporator for evaporating and condensing the refrigerant under an intermediate pressure between the condensing pressure of the condenser and the evaporating pressure of the evaporator 210. The low-temperature heat source fluid is successively cooled by the heat exchanging means, cooled by the evaporator, and heated by the heat exchanger in such order. The low-temperature heat source fluid can be precooled by the heat exchanger prior to cooling in the evaporator, and the amount of heat removed in the precooling process can be recovered from the low-temperature heat source fluid which has been cooled by the evaporator.
摘要翻译：具有高性能系数的热泵和除湿装置每消除水分消耗少量的能量。热泵包括用于提高制冷剂压力的加压器; 用于冷凝制冷剂以加热高温热源流体的冷凝器; 用于蒸发制冷剂以冷却低温热源流体的蒸发器; 以及热交换器，其设置在连接冷凝器和蒸发器的制冷剂路径中，用于在冷凝器的冷凝压力与蒸发器210的蒸发压力之间的中间压力下蒸发和冷凝制冷剂。低温热源流体依次冷却通过由蒸发器冷却的热交换装置，并按照这种顺序由热交换器加热。在蒸发器中冷却之前，低温热源流体可以由热交换器预冷却，并且可以从已经被蒸发器冷却的低温热源流体中回收在预冷却过程中除去的热量。

8. 发明授权

US07746711B2 Semiconductor device and semiconductor chips outputting a data strobe signal 有权
标题翻译：输出数据选通信号的半导体器件和半导体芯片
公开(公告)号：US07746711B2
公开(公告)日：2010-06-29
申请号：US11984606
申请日：2007-11-20
申请人： Hideo Inaba
发明人： Hideo Inaba
IPC分类号： G11C7/00
CPC分类号： G11C7/1027 , G11C7/1066 , G11C7/1072 , G11C7/22 , G11C11/4076
摘要： High-speed operation is achieved without increase in a circuit current and unstable operation of data strobe signal level due to collision between data strobe signals. Each of RAMs 11a and 11b outputs a data signal DQ and a data strobe signal DQS indicative of an output timing of the data signal. RAM 11a includes a strobe signal control unit 15a that determines whether RAM 11b connected in parallel with the RAM 11a is in a read state or not, and delays an output start timing of data strobe signal DQS when the RAM 11b is in the read state. Strobe signal control unit 15a of the RAM 11a controls output start timing so that a latter half portion of a preamble period of the data strobe signal DQS to be output coincides with a postamble period of the data strobe signal DQS output by the RAM 11b.
摘要翻译：由于数据选通信号之间的冲突，电路电流不增加，数据选通信号电平不稳定，实现高速运行。每个RAM11a和11b输出数据信号DQ和表示数据信号的输出定时的数据选通信号DQS。 RAM 11a包括选通信号控制单元15a，其确定与RAM 11a并联连接的RAM 11b是否处于读取状态，并且当RAM 11b处于读取状态时延迟数据选通信号DQS的输出开始定时。 RAM 11a的选通信号控制单元15a控制输出开始定时，使得要输出的数据选通信号DQS的前导码周期的后半部分与RAM 11b输出的数据选通信号DQS的后同步周期一致。

9. 发明申请

US20060245098A1 Actuator for valve lift controller 失效
公开(公告)号：US20060245098A1
公开(公告)日：2006-11-02
申请号：US11411152
申请日：2006-04-26
申请人： Yasuyoshi Suzuki , Hideo Inaba , Jouji Yamaguchi , Toshiki Fujiyoshi , Akira Tsunoda
发明人： Yasuyoshi Suzuki , Hideo Inaba , Jouji Yamaguchi , Toshiki Fujiyoshi , Akira Tsunoda
IPC分类号： G11B5/00
CPC分类号： F01L13/0015 , F01L1/185 , F01L1/2405 , F01L2820/032
摘要： A feed screw mechanism including a screwed shaft which moves linearly along with the control shaft, and a rotation spindle which rotates in a circumferential direction. The feed screw mechanism converts a rotational movement of the rotation spindle into a linear movement of the screwed shaft. A protrusion protrudes outwardly from the rotation spindle. An internal thread member engages with an outer wall surface of the rotation spindle. A motor stator generating a magnetic is positioned over the rotation spindle, and is sandwiched between the protrusion and the internal thread member in an axial direction of the rotation spindle.

10. 发明授权

US07100553B2 Actuator for valve lift control device having cam mechanism 失效
标题翻译：具有凸轮机构的气门升程控制装置的执行器
公开(公告)号：US07100553B2
公开(公告)日：2006-09-05
申请号：US11156487
申请日：2005-06-21
申请人： Yasuyoshi Suzuki , Akihiko Kameshima , Hideo Inaba , Jouji Yamaguchi
发明人： Yasuyoshi Suzuki , Akihiko Kameshima , Hideo Inaba , Jouji Yamaguchi
IPC分类号： F01L1/34
CPC分类号： F01L13/0063 , F01L1/044 , F01L1/08 , F01L1/185 , F01L1/2405 , F01L1/267 , F01L2105/00 , F01L2820/032 , F02D13/0207 , Y02T10/18 , Y10T74/2107
摘要： An actuator for a valve lift control device linearly moves a control shaft to change a valve lift in accordance with an axial position of the control shaft. A first and a second rotation cam integrally rotate around a common rotation axis by transmission of torque, so that a direct acting follower, which includes a first and a contact members, linearly moves with a control shaft. The first and a second rotation cams are respectively in contact with the first and the second contact members via a first and a second contact points. The first contact point is located on the opposite side of the second contact point with respect to the rotation axis. A sum of a first rotation cam lift of the first rotation cam and a second rotation cam lift of the second rotation cam is substantially constant in a predetermined rotation angular range of the first rotation cam and the second rotation cam.
摘要翻译：用于气门升程控制装置的致动器根据控制轴的轴向位置线性移动控制轴以改变气门升程。第一旋转凸轮和第二旋转凸轮通过扭矩的传递一体地围绕公共旋转轴旋转，使得包括第一和接触部件的直动随动件与控制轴线性地移动。第一和第二旋转凸轮分别经由第一和第二接触点与第一和第二接触构件接触。第一接触点相对于旋转轴线位于第二接触点的相反侧。第一旋转凸轮的第一旋转凸轮升程和第二旋转凸轮的第二旋转凸轮升程的总和在第一旋转凸轮和第二旋转凸轮的预定旋转角度范围内基本上恒定。

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