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    • 1. 发明授权
    • Memory control apparatus
    • 存储器控制装置
    • US07516254B2
    • 2009-04-07
    • US11470742
    • 2006-09-07
    • Hidenori NankiYoshiteru MinoKeizo Sumida
    • Hidenori NankiYoshiteru MinoKeizo Sumida
    • G06F5/00G06F13/28
    • G06F13/1631
    • A memory control apparatus is capable of surely becoming consistent with an external memory while avoiding a deterioration in access efficiency to the external memory. The memory control apparatus includes: a data buffer and an address buffer which respectively store data and addresses related to past access requests from a first master; a first comparison unit which compares a new address with the address of the address buffer upon receiving the new address; a buffer control unit which performs one of issuing an access request to an external memory I/F or outputting the data in the data buffer to the first master, depending on the comparison result; a specific access detection unit which disables the contents of the data buffer irrespective of the comparison result.
    • 存储器控制装置能够确保与外部存储器一致,同时避免对外部存储器的访问效率的劣化。 存储器控制装置包括:数据缓冲器和地址缓冲器,其分别存储与来自第一主机的过去访问请求相关的数据和地址; 第一比较单元,其在接收到新地址时将新地址与地址缓冲器的地址进行比较; 缓冲器控制单元,其根据比较结果执行向外部存储器I / F发出访问请求或将数据缓冲器中的数据输出到第一主机的一个; 特定访问检测单元,其与比较结果无关地禁用数据缓冲器的内容。