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1. 发明授权

US08264083B2 Semiconductor device and semiconductor device manufacturing method 失效
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US08264083B2
公开(公告)日：2012-09-11
申请号：US12548820
申请日：2009-08-27
申请人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
发明人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
IPC分类号： H01L23/48 , H01L23/52
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L27/105 , H01L27/11526 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.
摘要翻译：存储单元部分中的第一杂质扩散层和外围电路部分中的第二杂质扩散层设置在半导体衬底的表面中，并且具有大致彼此齐平的上表面。形成第一和第二绝缘膜以覆盖杂质扩散层的上表面，并且具有基本上均匀的膜厚度。第一金属插塞形成在绝缘膜中，并连接到第一杂质扩散层。第二金属插塞形成在第一绝缘膜中，具有比第一金属插塞低的高度，并且连接到第二杂质扩散层。第一金属互连件连接到第一金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。第二金属互连件连接到第二金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。

2. 发明申请

US20100052173A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE MANUFACTURING METHOD 失效
标题翻译：半导体器件和半导体器件制造方法
公开(公告)号：US20100052173A1
公开(公告)日：2010-03-04
申请号：US12548820
申请日：2009-08-27
申请人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
发明人： Hidefumi Nawata , Kikuko Sugimae , Akihiro Kajita , Takamichi Tsuchiya
IPC分类号： H01L23/532 , H01L21/768
CPC分类号： H01L23/53295 , H01L21/76802 , H01L21/76816 , H01L21/76877 , H01L21/76883 , H01L23/5226 , H01L23/53238 , H01L23/53266 , H01L27/105 , H01L27/11526 , H01L27/11573 , H01L2924/0002 , H01L2924/00
摘要： A first impurity diffusion layer in a memory cell portion and a second impurity diffusion layer in a peripheral circuit portion are provided in a surface of a semiconductor substrate and having upper faces substantially flush with each other. First and second insulating films are formed to cover the upper faces of the impurity diffusion layers, and having substantially uniform film thicknesses. A first metal plug is formed in the insulating films, and connected to the first impurity diffusion layer. A second metal plug is formed in the first insulating film, to have a lower height than the first metal plug, and is connected to the second impurity diffusion layer. A first metal interconnection is connected to an upper end portion of the first metal plug, and having an upper face embedded in and flush with the second insulating film. A second metal interconnection is connected to an upper end portion of the second metal plug, and having an upper face embedded in and flush with the second insulating film.
摘要翻译：存储单元部分中的第一杂质扩散层和外围电路部分中的第二杂质扩散层设置在半导体衬底的表面中，并且具有大致彼此齐平的上表面。形成第一和第二绝缘膜以覆盖杂质扩散层的上表面，并且具有基本上均匀的膜厚度。第一金属插塞形成在绝缘膜中，并连接到第一杂质扩散层。第二金属插塞形成在第一绝缘膜中，具有比第一金属插塞低的高度，并且连接到第二杂质扩散层。第一金属互连件连接到第一金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。第二金属互连件连接到第二金属插塞的上端部分，并且具有嵌入第二绝缘膜并与第二绝缘膜齐平的上表面。

3. 发明授权

US08599620B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08599620B2
公开(公告)日：2013-12-03
申请号：US13418881
申请日：2012-03-13
申请人： Hidefumi Nawata
发明人： Hidefumi Nawata
IPC分类号： G11C11/34
CPC分类号： G11C16/3418 , G11C16/0483 , G11C16/10
摘要： A nonvolatile semiconductor memory device according to an embodiment includes a control unit configured to perform a control of repeating a program operation, and a step-up operation, the program operation being an operation of applying a program pulse voltage to a selected memory cell and applying an intermediate voltage less than the program pulse voltage to first and second non-selected memory cells adjacent to the selected memory cell, and the step-up operation being an operation of increasing the program pulse voltage by a first step-up value. For a first period, the control unit maintains the intermediate voltage to be a constant value. For a second period, the control unit controls the step-up operation such that the intermediate voltage is increased by a second step-up value, and determines the first step-up value on the basis of the second step-up value.
摘要翻译：根据实施例的非易失性半导体存储器件包括：控制单元，被配置为执行重复编程操作的控制;以及升压操作，所述编程操作是将编程脉冲电压施加到所选择的存储单元并施加对与所选择的存储单元相邻的第一和第二非选择存储单元的编程脉冲电压小于编程脉冲电压的中间电压，升压操作是将编程脉冲电压增加第一升压值的操作。在第一时段中，控制单元将中间电压保持为恒定值。在第二时段中，控制单元控制升压操作使得中间电压增加第二升压值，并且基于第二升压值确定第一升压值。

4. 发明授权

US08873292B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US08873292B2
公开(公告)日：2014-10-28
申请号：US13424741
申请日：2012-03-20
申请人： Hidefumi Nawata , Kiyomi Naruke
发明人： Hidefumi Nawata , Kiyomi Naruke
IPC分类号： G11C11/34 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.
摘要翻译：根据一个实施例的非易失性半导体存储器件包括：存储单元; 连接到存储单元的字线; 以及控制电路，被配置为控制数据读取操作。当控制数据读取操作时，控制电路将一个读取电压施加到所选择的字线，将第一读取通过电压施加到连接到一个数据写入的存储器单元的第一个未选择的字线，并施加第二个读取将电压传递到连接到非写入存储单元的第二未选择字线。每个读取电压被设置为两个阈值电压分布之间的电压。第一读通过电压被设置为使得数据写入的存储器单元变为导通。第二读取通过电压被设置为低于最高读取电压，最高读取电压是读取电压中的最高电压。

5. 发明授权

US08659951B2 Nonvolatile semiconductor memory device and method of data write therein 失效
标题翻译：非易失性半导体存储器件及其中的数据写入方法
公开(公告)号：US08659951B2
公开(公告)日：2014-02-25
申请号：US13423708
申请日：2012-03-19
申请人： Hidefumi Nawata
发明人： Hidefumi Nawata
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3436
摘要： A bit line is electrically connected to one end of a current path of a memory cell. A word line is commonly connected to the memory cells arranged in a direction intersecting the bit line. A control circuit executes a write operation for applying a write voltage to the word line so shift a threshold voltage of the memory cell to be data written that the threshold voltage of the memory cell to be data written reaches a certain threshold voltage. During the write operation, the control circuit, while applying a gradually rising write voltage to the word line, gradually changes a voltage applied to the bit line based on a relationship between the threshold voltage of the memory cell to be written and a number of times of the write voltage applications.
摘要翻译：位线电连接到存储器单元的当前路径的一端。字线通常连接到沿与位线相交的方向排列的存储单元。控制电路执行用于向字线施加写入电压的写入操作，从而将要写入的数据的存储器单元的阈值电压移位为要写入数据的存储器单元的阈值电压达到一定的阈值电压。在写入操作期间，控制电路在向字线施加逐渐增加的写入电压的同时，基于要写入的存储器单元的阈值电压与次数之间的关系逐渐改变施加到位线的电压的写电压应用。

6. 发明申请

US20130077404A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20130077404A1
公开(公告)日：2013-03-28
申请号：US13424741
申请日：2012-03-20
申请人： Hidefumi Nawata , Kiyomi Naruke
发明人： Hidefumi Nawata , Kiyomi Naruke
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C16/3418 , G11C16/3454
摘要： A nonvolatile semiconductor memory device according to one embodiment includes: memory cells; word lines connected to the memory cells; and a control circuit configured to control a data read operation. When controlling the data read operation, the control circuit applies one of read voltages to a selected word line, applies a first read pass voltage to a first non-selected word line connected to one of data-written memory cells, and applies a second read pass voltage to a second non-selected word line connected to a non-written memory cell. Each of the read voltages is set to a voltage between two threshold voltage distributions. The first read pass voltage is set so that the data-written memory cells become conductive. The second read pass voltage is set so as to be lower than a highest read voltage, the highest read voltage being the highest voltage among the read voltages.
摘要翻译：根据一个实施例的非易失性半导体存储器件包括：存储单元; 连接到存储单元的字线; 以及控制电路，被配置为控制数据读取操作。当控制数据读取操作时，控制电路将一个读取电压施加到所选择的字线，将第一读取通过电压施加到连接到数据写入存储器单元之一的第一未选择字线，并施加第二读取将电压传递到连接到非写入存储单元的第二未选择字线。每个读取电压被设置为两个阈值电压分布之间的电压。第一读通过电压被设置为使得数据写入的存储器单元变为导通。第二读取通过电压被设置为低于最高读取电压，最高读取电压是读取电压中的最高电压。

7. 发明授权

US08406049B2 Nonvolatile semiconductor memory device and writing method thereof 失效
标题翻译：非易失性半导体存储器件及其写入方法
公开(公告)号：US08406049B2
公开(公告)日：2013-03-26
申请号：US13020401
申请日：2011-02-03
申请人： Hidefumi Nawata
发明人： Hidefumi Nawata
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C11/5628 , G11C16/3418
摘要： A control circuit is configured to execute a writing operation for giving a second threshold voltage distribution to a plurality of memory cells formed along one word line. In the writing operation, the control circuit performs a writing operation by executing a voltage applying operation in memory cells to be given the second threshold voltage distribution. While the control circuit executes a voltage applying operation in memory cells to be maintained in an erased state, thereby moving a first threshold voltage distribution to a positive direction to obtain a third threshold voltage distribution representing the erased state.
摘要翻译：控制电路被配置为执行用于给沿着一个字线形成的多个存储单元提供第二阈值电压分布的写入操作。在写入操作中，控制电路通过在存储单元中执行施加电压来执行写入操作以被赋予第二阈值电压分布。当控制电路在保持在擦除状态的存储单元中执行电压施加操作时，由此将第一阈值电压分布移动到正方向以获得表示擦除状态的第三阈值电压分布。

8. 发明授权

US08599610B2 Non-volatile semiconductor storage device having a control circuit configured to execute a read operation 失效
标题翻译：具有被配置为执行读取操作的控制电路的非易失性半导体存储器件
公开(公告)号：US08599610B2
公开(公告)日：2013-12-03
申请号：US13223685
申请日：2011-09-01
申请人： Hidefumi Nawata
发明人： Hidefumi Nawata
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/28 , G11C16/3427
摘要： A non-volatile semiconductor storage device according to an embodiment includes a memory cell array and a control circuit configured to execute a read operation. The control circuit refers to data of a reference memory cell which is adjacent to a selected memory cell and in which data is written after a data write operation on the selected memory cell. The control circuit applies a first read pass voltage to a non-selected word line adjacent to the selected word line, when the data of the reference memory cell is data causing the shift of the threshold voltage of the selected memory cell. The control circuit applies a second read pass voltage lower than the first read pass voltage to the non-selected word line, when the data of the reference memory cell is data not causing the shift of the threshold voltage of the selected memory cell.
摘要翻译：根据实施例的非易失性半导体存储装置包括被配置为执行读取操作的存储单元阵列和控制电路。控制电路是指与所选择的存储单元相邻的参考存储单元的数据，并且在对选择的存储单元进行数据写入操作之后写入数据。当参考存储单元的数据是导致所选存储单元的阈值电压偏移的数据时，控制电路将第一读通道电压施加到与所选字线相邻的未选字线。当参考存储单元的数据是不导致所选存储单元的阈值电压偏移的数据时，控制电路将低于第一读通过电压的第二读通过电压施加到未选择的字线。

9. 发明授权

US08576623B2 Non-volatile semiconductor storage device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US08576623B2
公开(公告)日：2013-11-05
申请号：US13223891
申请日：2011-09-01
申请人： Hidefumi Nawata
发明人： Hidefumi Nawata
IPC分类号： G11C16/04 , G11C16/34
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/28 , G11C16/3404
摘要： A non-volatile semiconductor storage device according to one embodiment includes a memory cell array that has NAND cell units in which a plurality of memory cells are connected in series, the control gate of each of the plurality of memory cells being connected to a word line, and a control circuit configured to execute a write operation by applying a write voltage to the word line. The control circuit is configured to execute a correction write operation accompanied by the write operation and executed on a selected memory cell, when a threshold voltage of data written in a reference memory cell is an erase level, the reference memory cell being the memory cell adjacent to the selected memory cell and in which the data is written after the write operation on the selected memory cell.
摘要翻译：根据一个实施例的非易失性半导体存储装置包括存储单元阵列，其具有多个存储单元串联连接的NAND单元单元，多个存储单元中的每一个的控制栅极连接到字线以及控制电路，被配置为通过向字线施加写入电压来执行写入操作。控制电路被配置为当写入参考存储单元的数据的阈值电压为擦除电平时，执行伴随着写入操作并在所选存储单元上执行的校正写入操作，该参考存储器单元是相邻的存储器单元到所选择的存储单元，并且在对所选存储单元进行写操作之后写入数据。

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