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1. 发明申请

US20050151277A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050151277A1
公开(公告)日：2005-07-14
申请号：US11035592
申请日：2005-01-13
申请人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Hidetoshi Masuda , Toshimasa Suzuki
发明人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Hidetoshi Masuda , Toshimasa Suzuki
IPC分类号： H01L27/105 , G11C13/00 , G11C16/02 , H01L27/115 , H01L27/24 , H01L45/00 , H01L27/11
CPC分类号： H01L27/2436 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/78 , G11C2213/79 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641
摘要： A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.
摘要翻译：通过依次层叠下电极，可变电阻器和上电极来形成非易失性存储元件。形成结晶性和非晶态混合的可变电阻器。因此，形成非易失性存储元件。更优选地，可变电阻器是由通式为Pr 1-x M x MnO 3 N 3表示的镨 - 钙 - 锰氧化物，在350℃至500℃的成膜温度下形成的可变电阻器。或者，可变电阻器以允许可变电阻器变为非晶态的成膜温度或结晶度的状态形成为膜并且将非晶化混合，然后在可变电阻器可以保持结晶性和非晶态混合的状态的温度范围内，在高于成膜温度的温度下进行退火处理。

2. 发明授权

US07259387B2 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US07259387B2
公开(公告)日：2007-08-21
申请号：US11035592
申请日：2005-01-13
申请人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Hidetoshi Masuda , Toshimasa Suzuki
发明人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Hidetoshi Masuda , Toshimasa Suzuki
IPC分类号： H01L47/00
CPC分类号： H01L27/2436 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/78 , G11C2213/79 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625 , H01L45/1641
摘要： A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.
摘要翻译：通过依次层叠下电极，可变电阻器和上电极来形成非易失性存储元件。形成结晶性和非晶态混合的可变电阻器。因此，形成非易失性存储元件。更优选地，可变电阻器是由通式为Pr 1-x M x MnO 3 N 3表示的镨 - 钙 - 锰氧化物，在350℃至500℃的成膜温度下形成的可变电阻器。或者，可变电阻器以允许可变电阻器变为非晶态的成膜温度或结晶度的状态形成为膜并且将非晶化混合，然后在可变电阻器可以保持结晶性和非晶态混合的状态的温度范围内，在高于成膜温度的温度下进行退火处理。

3. 发明授权

US07045840B2 Nonvolatile semiconductor memory device comprising a variable resistive element containing a perovskite-type crystal structure 有权
标题翻译：包括含有钙钛矿型晶体结构的可变电阻元件的非易失性半导体存储器件
公开(公告)号：US07045840B2
公开(公告)日：2006-05-16
申请号：US11001744
申请日：2004-12-01
申请人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
发明人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
IPC分类号： H01L29/76
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.
摘要翻译：在包括通过顺序堆叠下电极，具有钙钛矿型晶体结构的可变电阻器和上电极形成的可变电阻元件的非易失性半导体存储器件中，下电极和上电极中的至少一个是颗粒电极被配置为包括颗粒状导体集合体，使得在界面处与可变电阻器的接触面积被有效地减小以实现可变电阻元件的高初始电阻。此外，可变电阻器的膜优选形成为高度结晶的状态。

4. 发明申请

US20050145910A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050145910A1
公开(公告)日：2005-07-07
申请号：US11001744
申请日：2004-12-01
申请人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
发明人： Yukio Tamai , Nobuyoshi Awaya , Shinji Kobayashi , Hidechika Kawazoe , Toshimasa Suzuki , Hidetoshi Masuda , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
IPC分类号： H01L27/10 , G11C13/00 , H01L21/8234 , H01L29/76 , H01L45/00
CPC分类号： G11C13/0007 , G11C2213/31 , G11C2213/52 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/1253 , H01L45/147 , H01L45/1625
摘要： In a nonvolatile semiconductor memory device including a variable resistive element formed by sequentially stacking a lower electrode, a variable resistor with a perovskite-type crystal structure, and an upper electrode, at least one of the lower electrode and the upper electrode is a particulate electrode configured to include a particulate conductor aggregate, so that the contact area with the variable resistor at an interface is effectively reduced to realize high initial resistance of the variable resistive element. Further, a film of the variable resistor is preferably formed so as to be in a highly crystalline state.
摘要翻译：在包括通过顺序堆叠下电极，具有钙钛矿型晶体结构的可变电阻器和上电极形成的可变电阻元件的非易失性半导体存储器件中，下电极和上电极中的至少一个是颗粒电极被配置为包括颗粒状导体集合体，使得与界面处的可变电阻器的接触面积被有效地减小以实现可变电阻元件的高初始电阻。此外，可变电阻器的膜优选形成为高度结晶的状态。

5. 发明申请

US20050153504A1 Method for manufacturing nonvolatile semiconductor memory device 审中-公开
标题翻译：非易失性半导体存储器件的制造方法
公开(公告)号：US20050153504A1
公开(公告)日：2005-07-14
申请号：US11035089
申请日：2005-01-12
申请人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
发明人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Naoto Hagiwara , Yuji Matsushita , Yuji Nishi
IPC分类号： H01L27/10 , G11C13/00 , H01L21/02 , H01L21/8246 , H01L21/8247 , H01L27/112 , H01L27/115 , H01L27/24 , H01L29/68 , H01L45/00 , H01L21/8238
CPC分类号： H01L45/1675 , G11C13/0007 , G11C13/003 , G11C2213/31 , G11C2213/78 , G11C2213/79 , H01L27/2436 , H01L45/04 , H01L45/1233 , H01L45/147 , H01L45/1625
摘要： In a manufacturing method of a nonvolatile semiconductor memory device including a variable resistive element having a variable resistor made of a perovskite-type metal oxide film, the variable resistor is formed at a temperature which is lower than the melting point of a metal wire layer that has been formed before formation of the variable resistor. More preferably, the variable resistor is formed by a praseodymium calcium manganese oxide, which is represented by a general formula, Pr1-xCaxMnO3, carried out at a film forming temperature in a range from 350° C. to 500° C. according to a sputtering method.
摘要翻译：在包括具有由钙钛矿型金属氧化物膜制成的可变电阻器的可变电阻元件的非易失性半导体存储器件的制造方法中，可变电阻器形成在低于金属线层的熔点的温度，在形成可变电阻器之前形成。更优选地，可变电阻器由镨钙锰氧化物形成，所述镨钙锰氧化物由通式Ⅺ1-x≡MMn O 3 根据溅射法在350℃至500℃的范围内的成膜温度下进行。

6. 发明授权

US07697317B2 Nonvolatile semiconductor memory device 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US07697317B2
公开(公告)日：2010-04-13
申请号：US11913490
申请日：2006-04-26
申请人： Atsushi Shimaoka , Hidechika Kawazoe , Yukio Tamai
发明人： Atsushi Shimaoka , Hidechika Kawazoe , Yukio Tamai
IPC分类号： G11C11/00 , G11C11/14 , G11C11/15
CPC分类号： G11C13/00 , G11C8/08 , G11C13/0028 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/77 , H01L27/101
摘要： A nonvolatile semiconductor storage device is provided with a memory cell selecting circuit which selects a selected memory cell from a memory cell array; and a write voltage applying circuit, which applies a row write voltage and a column write voltage to a selected word line and a selected bit line, respectively, and applies a row write blocking voltage and a column write blocking voltage to an unselected word line and an unselected bit line, respectively, and applies a write voltage sufficient for writing only on both ends of the selected memory cell. The write voltage applying circuit applies a write compensating voltage, which has a polarity opposite to that of the voltage applied on the both ends of the unselected memory cells other than the selected memory cell, on both ends of the unselected memory cells, while the write voltage is applied to the selected memory cell.
摘要翻译：非易失性半导体存储装置具有存储单元选择电路，其从存储单元阵列中选择选定的存储单元; 以及写入电压施加电路，其分别对所选择的字线和选定的位线施加行写入电压和列写入电压，并向未选择的字线施加行写入阻塞电压和列写入阻塞电压，分别是未选择的位线，并且施加足以仅写入所选择的存储器单元的两端的写电压。写入电压施加电路在未选择的存储单元的两端上施加写入补偿电压，该补偿电压具有与所选存储单元以外的未选择的存储单元的两端上施加的电压的极性相反的写入补偿电压，而写入电压被施加到所选择的存储单元。

7. 发明授权

US07535746B2 Nonvolatile semiconductor memory device and read method 有权
标题翻译：非易失性半导体存储器件和读取方法
公开(公告)号：US07535746B2
公开(公告)日：2009-05-19
申请号：US11191900
申请日：2005-07-27
申请人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Hidenori Morimoto , Nobuyoshi Awaya
发明人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Hidenori Morimoto , Nobuyoshi Awaya
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , G11C2213/79
摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.
摘要翻译：根据本发明的非易失性半导体存储器件包括存储单元选择电路，用于以行，列或存储单元为单位从存储单元阵列中选择存储单元; 读取电压施加电路，用于对由存储单元选择电路选择的所选存储单元的可变电阻元件施加读取电压; 以及读取电路，用于根据可变电阻器元件的电阻值相对于要选择的存储器单元读取的存储单元检测流过的读取电流的量并读取存储在待读取的存储器单元中的信息 ; 并且读取电压施加电路将具有与读取电压相反的极性的虚拟读取电压施加到所选存储单元的可变电阻器元件。

8. 发明申请

US20090046495A1 NONVOLATILE SEMICONDUCTOR MEMORY DEVICE 失效
标题翻译：非易失性半导体存储器件
公开(公告)号：US20090046495A1
公开(公告)日：2009-02-19
申请号：US11913490
申请日：2006-04-26
申请人： Atsushi Shimaoka , Hidechika Kawazoe , Yukio Tamai
发明人： Atsushi Shimaoka , Hidechika Kawazoe , Yukio Tamai
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/00 , G11C8/08 , G11C13/0028 , G11C13/0069 , G11C2013/0073 , G11C2013/009 , G11C2213/77 , H01L27/101
摘要： A nonvolatile semiconductor memory device comprises a memory cell selecting circuit which selects a selected memory cell (M0) from a memory cell array (3); and a programming voltage applying circuit, which applies a row programming voltage and a column programming voltage to a selected word line and a selected bit line, respectively, and applies a row programming blocking voltage and a column programming blocking voltage to unselected word lines and unselected bit lines, respectively, and applies a programming voltage sufficient for programming only on both ends of the selected memory (M0). The programming voltage applying circuit applies a programming compensating voltage having a polarity opposite to that of the voltage applied on both ends of the unselected memory cells (M1, M2) other than the selected memory cell (M0), on both ends of the unselected memory cells (M1, M2), while the programming voltage is applied to the selected memory cell (M0).
摘要翻译：非易失性半导体存储器件包括从存储单元阵列（3）中选择所选存储单元（M0）的存储单元选择电路; 以及编程电压施加电路，其分别对所选择的字线和选定的位线施加行编程电压和列编程电压，并对未选择的字线和未选择的字线施加行编程阻止电压和列编程阻塞电压并且仅在所选择的存储器（M0）的两端施加足以进行编程的编程电压。编程电压施加电路施加与非选择存储器（M0）以外的未被选择的存储单元（M1，M2）的两端施加的电压极性相反的编程补偿电压，在未选择的存储器而编程电压被施加到所选存储单元（M0）时，单元（M1，M2）。

9. 发明申请

US20060023497A1 Nonvolatile semiconductor memory device and read method 有权
公开(公告)号：US20060023497A1
公开(公告)日：2006-02-02
申请号：US11191900
申请日：2005-07-27
申请人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Hidenori Morimoto , Nobuyoshi Awaya
发明人： Hidechika Kawazoe , Yukio Tamai , Atsushi Shimaoka , Hidenori Morimoto , Nobuyoshi Awaya
IPC分类号： G11C11/00
CPC分类号： G11C13/0007 , G11C13/004 , G11C2213/31 , G11C2213/77 , G11C2213/79
摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

10. 发明授权

US07978495B2 Nonvolatile semiconductor storage device and method for operating same 有权
标题翻译：非易失性半导体存储装置及其操作方法
公开(公告)号：US07978495B2
公开(公告)日：2011-07-12
申请号：US11883552
申请日：2006-01-05
申请人： Hidechika Kawazoe , Yukio Tamai
发明人： Hidechika Kawazoe , Yukio Tamai
IPC分类号： G11C11/00
CPC分类号： G11C13/0021 , G11C13/0002 , G11C13/0007 , G11C13/004 , G11C13/0069 , G11C2213/31
摘要： A nonvolatile semiconductor memory device for suppressing a current consumption caused by a transient current because of the potential change of the bit and word lines at the time of shifting between the programming, reading, and erasing actions in a highly integrated memory cell array is provided. A memory cell (1) array comprises two-terminal memory cells each having a variable resistance element whose resistance value reversibly changes by pulse application are arranged in a row and column directions, wherein the memory cells in a row are connected at one end to common word lines (WL1 to WLn), the memory cells in a column are connected at the other end to common bit lines (BL1 to BLm), and a common unselected voltage VWE/2 is applied to both unselected word and bit lines not connected to the selected memory cell during the reading, programming, and erasing actions for the selected memory cell.
摘要翻译：提供一种用于抑制由于在高度集成的存储单元阵列中的编程，读取和擦除动作之间移位时的位和字线的电位变化而导致的由瞬态电流引起的电流消耗的非易失性半导体存储器件。存储单元（1）阵列包括两端存储单元，每个二端存储单元都具有可变电阻元件，其电阻值通过脉冲施加可逆地改变，排列成行和列方向，其中一行中的存储单元一端连接到公共端字线（WL1〜WLn）中，列的存储单元在另一端连接到公共位线（BL1〜BLm），公共未选择电压VWE / 2被施加到未连接的未选择字和位线在所选存储单元的读取，编程和擦除操作期间所选存储单元。

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