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1. 发明授权

US5349381A Video camera with aperture correction having reduced power consumption 失效
标题翻译：具有孔径校正的摄像机具有降低的功耗
公开(公告)号：US5349381A
公开(公告)日：1994-09-20
申请号：US23931
申请日：1993-02-26
申请人： Hideaki Murayama , Taku Kihara , Fumihiko Sudo , Takashi Asaida
发明人： Hideaki Murayama , Taku Kihara , Fumihiko Sudo , Takashi Asaida
IPC分类号： H04N9/04 , H04N5/225 , H04N5/208
CPC分类号： H04N9/045 , H04N2209/046
摘要： In a video camera having three image pickup devices in which a pixel of one channel of channels forming three primary colors is spatially displaced from other pixels of two channels by 1/2 pixel, when three primary color signals output from the three image pickup devices are converted into digital three primary color signals, an aperture signal is formed from the digital three primary color signals, the aperture signal output is added to the digital three primary color signals and a digital video signal of a predetermined format is formed from the added signal, a clock frequency of an aperture signal forming circuit is set to be twice the clock frequencies of the image pickup devices, an A/D converting circuit and a video signal forming circuit.
摘要翻译：在具有三个图像拾取装置的摄像机中，其中形成三原色的一个通道的像素与两个通道的其他像素空间位移1/2像素，当从三个图像拾取装置输出的三个原色信号是转换为数字三原色信号，通过数字三原色信号形成孔径信号，将孔径信号输出添加到数字三原色信号，并从加入的信号形成预定格式的数字视频信号，孔径信号形成电路的时钟频率被设定为图像拾取器件，A / D转换电路和视频信号形成电路的时钟频率的两倍。

2. 发明授权

US5272536A Dark current and defective pixel correction apparatus 失效
标题翻译：暗电流和缺陷像素校正装置
公开(公告)号：US5272536A
公开(公告)日：1993-12-21
申请号：US668251
申请日：1991-03-12
申请人： Fumihiko Sudo , Takashi Asaida
发明人： Fumihiko Sudo , Takashi Asaida
IPC分类号： H04N5/217 , H04N5/335
CPC分类号： H04N5/217
摘要： A dark current correction apparatus eliminates a dark current signal component or components from an output signal of an imaging device having an array of pixels. The apparatus includes an A/D converter for digitizing the output signal, and a memory for storing level data of the digitized signal while exposure of the imaging device is controlled to be at a zero level or a uniformly illuminated level, according to whether dark current correction or white current correction, respectively, is to be performed. A dark current correction signal former generates a dark current correction signal or signals from data read out from the memory. The dark current correction signal or signals are applied to a correction circuit which processes an output signal produced by the imaging device during normal imaging operation in accordance with the correction signal or signals in order to eliminate the dark current signal component or components from that output signal.

3. 发明授权

US5144446A Image defect correcting circuit for a solid state imager 失效
标题翻译：用于固态图像的图像缺陷校正电路
公开(公告)号：US5144446A
公开(公告)日：1992-09-01
申请号：US647715
申请日：1991-01-29
申请人： Fumihiko Sudo , Takashi Asaida
发明人： Fumihiko Sudo , Takashi Asaida
IPC分类号： H04N5/367
CPC分类号： H04N5/367
摘要： An image defect correcting circuit for a solid state imager arranged such that levels of output signals form respective pixels of a solid state image pickup element illuminated on its whole surface a light of uniform brightness are compared with a predetermined level, data indicative of a position of a pixel which outputs a signal of peculiar level is generated on the basis of a compared result, a video signal output from at least the pixel located at the position indicated by the position data is interpolated by using output signals of other pixels according to an interpolation processing and the output signals of the respective pixels and the video signal generated by the interpolation processing are selectively output on the basis of the position data.

4. 发明授权

US5512894A Rate converter for converting data rate 失效
标题翻译：用于转换数据速率的速率转换器
公开(公告)号：US5512894A
公开(公告)日：1996-04-30
申请号：US76839
申请日：1993-06-15
申请人： Hiromasa Ikeyama , Takashi Asaida
发明人： Hiromasa Ikeyama , Takashi Asaida
IPC分类号： H04N5/46 , H03H17/06 , H04N7/01 , H04N9/00 , H04N11/20 , H03M7/00
CPC分类号： H03H17/0685 , H04N7/0102
摘要： A rate converter for converting data rate is adapted to hold, at an output clock rate, by using a plurality of latch circuits, respective signals from the output stages of a shift register operative at an input clock rate to multiply, at the output clock rate by using a plurality of multipliers, held signals from the latch circuits by filter coefficients that a plurality of coefficient generators sequentially generate to add the multiplied outputs by using an adder to provide a rate converted output signal. Thus, this rate converter makes it possible to carry out rate conversion by a single digital filter without necessity of digital filters operative at a clock rate of the least common multiple of the input clock rate and the output clock rate.
摘要翻译：用于转换数据速率的速率转换器适于以输出时钟速率通过使用多个锁存电路来保持来自以输入时钟速率工作的移位寄存器的输出级的各个信号以输出时钟速率通过使用多个乘法器，通过多个系数发生器顺序产生的滤波器系数来从锁存电路获得保持的信号，以通过使用加法器来相加输出以提供一个速率变换的输出信号。因此，该速率转换器使得可以通过单个数字滤波器进行速率转换，而不需要以输入时钟速率和输出时钟速率的最小公倍数的时钟速率工作的数字滤波器。

5. 发明授权

US5408266A Bi-directional rate converting apparatus for converting a clock rate of a digital signal 失效
标题翻译：用于转换数字信号的时钟速率的双向速率转换装置
公开(公告)号：US5408266A
公开(公告)日：1995-04-18
申请号：US189640
申请日：1994-02-01
申请人： Hiromasa Ikeyama , Takashi Asaida
发明人： Hiromasa Ikeyama , Takashi Asaida
IPC分类号： H04N5/232 , H03H17/00 , H03H17/02 , H03H17/06 , H04N7/01 , H04N9/04
CPC分类号： H03H17/0657 , H03H17/0664 , H04N7/01 , H04N7/0102
摘要： Bi-directional rate converting apparatus up-converts a digital signal having a clock rate f.sub.B to a digital signal having a clock rate f.sub.A and also down-converts a digital signal having a clock rate f.sub.A to a digital signal having the clock rate f.sub.B. The digital signal having the clock rate f.sub.B is interpolated to produce a signal having the clock rate f.sub.A which is supplied to a filter during up-conversion. The digital signal having the clock rate f.sub.A is supplied to the filter during down-conversion, which after being filtered is thinned to produce a digital signal having the clock rate f.sub.B. The digital signal supplied to the filter is filtered in accordance with a frequency characteristic which has "0" points at frequencies of (f.sub.C /M)*x, where x equals an integer value from 1 to (M-1), and which also has "0" points at frequencies of (f.sub.C /L)*y, where y equals an integer value from 1 to (L-1). The value f.sub.C being the least common multiple of f.sub.A and f.sub.B such that f.sub.C =M*f.sub.A =L*f.sub.B, where M and L have respective integer values.
摘要翻译：双向速率转换装置将具有时钟频率fB的数字信号上变频到具有时钟速率fA的数字信号，并将具有时钟速率fA的数字信号下变频为具有时钟频率fB的数字信号。具有时钟速率fB的数字信号被内插以产生具有在上变换期间提供给滤波器的时钟速率fA的信号。具有时钟速率fA的数字信号在下变频期间被提供给滤波器，其在被滤波后被减薄以产生具有时钟频率fB的数字信号。提供给滤波器的数字信号根据频率为（fC / M）* x的“0”点的频率特性进行滤波，其中x等于从1到（M-1）的整数值，并且还在（fC / L）* y的频率处具有“0”点，其中y等于从1到（L-1）的整数值。值fC是fA和fB的最小公倍数，使得fC = M * fA = L * fB，其中M和L具有相应的整数值。

6. 发明授权

US4761685A Apparatus and method for solid-state image sensor element registration adjustment 失效
标题翻译：用于固态图像传感器元件配准调整的装置和方法
公开(公告)号：US4761685A
公开(公告)日：1988-08-02
申请号：US032518
申请日：1987-02-17
申请人： Takashi Asaida , Kenichi Aihara
发明人： Takashi Asaida , Kenichi Aihara
IPC分类号： H04N5/335 , H04N5/372 , H04N9/04 , H04N9/093 , H04N17/00
CPC分类号： H04N9/093
摘要： An apparatus and method for registration adjustment are disclosed, in which when effecting so-called registration adjustment for positioning solid-state image sensor element (31r, 31g and 31b) used for a solid-state image sensor apparatus at predetermined positions of an image sensor optical system (30), a registration adjustment test chart (10) having at least one horizontal or vertical shade recurrence pattern at a recurrence pitch (.tau.p) in a particular relation to the picture element pitch (.tau.c) of the solid-state image sensor elements (31r, 31g and 31b) is imaged, and the positional deviation in six directions of the solid-state image sensor elements (31r, 31g and 31b) is measured on the basis of the beat component of the image sensor output of the solid-state image sensor elements (31r, 31g and 31b) based on the difference between the picture element pitch (.tau.c) and the shade recurrence pitch (.tau.px).
摘要翻译： PCT No.PCT / JP86 / 00302 Sec。 371日期1987年2月17日 102（e）1987年2月17日PCT PCT 1986年6月17日PCT公布。公开号WO86 / 07660 日本公报1986年12月31日。公开了一种用于对准调整的装置和方法，其中当进行所谓的用于固定图像传感器装置的固态图像传感器元件（31r，31g和31b）的定位调整在图像传感器光学系统（30）的预定位置处，具有与图像元素间距特别关系的重复间距（τp）具有至少一个水平或垂直色度重现图案的对准调整测试图（10） c）成像固体摄像元件（31r，31g，31b），根据拍子测量固体摄像元件（31r，31g，31b）的6个方向的位置偏差基于图像元素间距（τc）与阴影重复间距（tau px）之间的差异，固体图像传感器元件（31r，31g和31b）的图像传感器输出的分量。

7. 发明授权

US4527191A Digital signal processing circuit 失效
标题翻译：数字信号处理电路
公开(公告)号：US4527191A
公开(公告)日：1985-07-02
申请号：US465053
申请日：1983-02-09
申请人： Fumio Nagumo , Takashi Asaida
发明人： Fumio Nagumo , Takashi Asaida
IPC分类号： H04N9/65 , G06F7/50 , G06F7/505 , H04N9/09 , H04N9/64 , H04N9/67 , H04N11/04 , H04N9/539
CPC分类号： G06F7/505 , H04N11/04 , H04N9/09 , H04N9/67 , G06F2207/388
摘要： A digital signal processing circuit, for example, a digital signal adder circuit suitable for use in a digital color encoder for generating a digital composite color video signal from three digital primary color signals. At least two input digital signals are respectively supplied to a signal delay circuit which generates the digital signal in the form of skew bits wherein the higher bit is given a larger delay. The output signals of the signal delay circuit are supplied to an adder circuit in which the small number of bits of the digital signals are added during one clock interval. And, the output signal of the adder circuit is supplied to a further delay circuit which generates a digital signal in the form of linear bits wherein any bit in originally the same clock interval is given the same delay.
摘要翻译：数字信号处理电路，例如适用于数字彩色编码器的数字信号加法器电路，用于从三个数字原色信号产生数字复合彩色视频信号。至少两个输入数字信号被分别提供给信号延迟电路，该信号延迟电路以偏斜位的形式生成数字信号，其中较高的位被给予更大的延迟。信号延迟电路的输出信号被提供给加法器电路，其中在一个时钟间隔期间相加数字信号的位数较少。并且，加法器电路的输出信号被提供给另一个延迟电路，该延迟电路产生线性位形式的数字信号，其中原始相同时钟间隔中的任何位被给予相同的延迟。

8. 发明授权

US5801772A Digital video camera apparatus and aspect ratio converting apparatus 失效
标题翻译：数字摄像机和纵横比变换装置
公开(公告)号：US5801772A
公开(公告)日：1998-09-01
申请号：US835114
申请日：1997-04-04
申请人： Takashi Asaida , Takashi Kameyama
发明人： Takashi Asaida , Takashi Kameyama
IPC分类号： H04N5/262 , H04N5/44 , H04N7/01 , H04N5/228 , H04N11/20
CPC分类号： H04N7/0122 , H04N5/2628 , H04N7/0102 , H04N7/0105
摘要： In a time axis converting section 10, time axis conversion processing of 4/3 times is implemented to a digital picture signal of a first data rate indicating an image of a first aspect ratio (16:9) to thereby generate a digital picture signal of a second data rate indicating an image of a second aspect ratio (4:3). In a data rate converting section 20, data rate conversion processing of conversion ratio of 3:4 is implemented to the digital picture signal of the second data rate to thereby generate, from the digital picture signal of the first data rate indicating the image of the first aspect ratio (16:9), a digital picture signal of a first data rate indicating the image of the second aspect ratio (4:3).
摘要翻译：在时间轴转换部10中，将表示第一宽高比（16:9）的图像的第一数据速率的数字图像信号实现为4/3次的时间轴转换处理，从而生成数字图像信号指示第二宽高比（4:3）的图像的第二数据速率。在数据速率转换部分20中，对第二数据速率的数字图像信号实现3:4的转换比率的数据速率转换处理，从而产生指示图像的第一数据速率的数字图像信号第一长宽比（16：9），表示第二宽高比（4:3）的图像的第一数据速率的数字图像信号。

9. 发明授权

US5521637A Solid state image pick-up apparatus for converting the data clock rate of the generated picture data signals 失效
标题翻译：用于转换所生成的图像数据信号的数据时钟速率的固态图像拾取装置
公开(公告)号：US5521637A
公开(公告)日：1996-05-28
申请号：US503424
申请日：1995-07-17
申请人： Takashi Asaida , Jun Hattori
发明人： Takashi Asaida , Jun Hattori
IPC分类号： H04N5/335 , H04N5/372 , H04N5/76 , H04N5/77 , H04N7/01 , H04N9/04 , H04N9/64 , H04N9/77 , H04N9/79 , H04N9/804 , H04N5/228
CPC分类号： H04N5/332 , H04N5/335 , H04N5/772 , H04N7/0105 , H04N9/045 , H04N9/64 , H04N9/7904 , H04N9/804 , H04N2209/049 , H04N5/77
摘要： A solid-state image pickup apparatus for generating image pickup signals produced by a solid-state image sensor. The image sensor is driven at a data rate of f.sub.s1 with a predetermined phase. Digital luminance signal Y and two digital chrominance signals C.sub.R, C.sub.B are generated by a first digital processing unit, operated at a clock rate related to the data rate of f.sub.s1, from the digitized image pickup signals. These signals are then converted by a second digital processing unit into signals Y, C.sub.R and C.sub.B having a data rate related to f.sub.s2. The second digital processing unit performs bandwidth limitations on these signals by a half band filter having a passband f.sub.s2, f.sub.s2 /2 and f.sub.s2 /2 and performs data rate conversion of from 2f.sub.s1 to f.sub.s2, from f.sub.s1 to f.sub.s2 /2 or f.sub.s2 /4 and from f.sub.s1 to f.sub.s2 /2 or f.sub.s2 /4, for outputting the low order linear phase finite impulse response sufficient to suppress high-order sideband components in the vicinity of n.multidot.2f.sub.s1, n.multidot.f.sub. s1, and n.multidot.f.sub.s1, (n being a positive integer) in a form that can be down-sampled at f.sub.s2, f.sub.s2 /2 or f.sub.s2 /4 and f.sub.s2 /2 or f.sub.s2 /4. The second digital processing unit can have a simplified construction when the characteristics of the half band filter are used to compensate for the band pass rollover characteristics of the rate-converting filter.
摘要翻译：一种用于产生由固态图像传感器产生的图像拾取信号的固态图像拾取装置。以预定相位的fs1的数据速率驱动图像传感器。数字亮度信号Y和两个数字色度信号CR，CB由数字化图像拾取信号由与数据速率fs1相关的时钟速率操作的第一数字处理单元产生。然后，这些信号被第二数字处理单元转换成具有与fs2相关的数据速率的信号Y，CR和CB。第二数字处理单元通过具有通带fs2，fs2 / 2和fs2 / 2的半带滤波器对这些信号执行带宽限制，并且执行从fs1到fs2 / 2或fs2 / 4从2fs1到fs2的数据速率转换 fs1至fs2 / 2或fs2 / 4，用于输出足以抑制nx2fs1，nxf s1和nxfs1附近的高阶边带分量的低阶线性相位有限脉冲响应，（n为正整数）可以在fs2，fs2 / 2或fs2 / 4和fs2 / 2或fs2 / 4下采样。当使用半波段滤波器的特性来补偿速率转换滤波器的带通翻转特性时，第二数字处理单元可以具有简化的结构。

10. 发明授权

US5299023A Portable video camera and recording apparatus 失效
标题翻译：便携式摄像机和录像设备
公开(公告)号：US5299023A
公开(公告)日：1994-03-29
申请号：US913359
申请日：1992-07-15
申请人： Fumio Nagumo , Takashi Asaida , Kenji Nakamura , Yoshio Chiba
发明人： Fumio Nagumo , Takashi Asaida , Kenji Nakamura , Yoshio Chiba
IPC分类号： H04N9/79 , H04N5/77 , H04N9/797 , H04N9/804 , H04N9/808 , H04N9/825 , H04N9/86 , H04N9/80
CPC分类号： H04N9/825 , H04N9/797 , H04N9/86 , H04N5/772 , Y10S358/906
摘要： A portable video camera and recording apparatus is comprised of a video camera section and a recording section. The video camera section is comprised of a CCD, analogue-to-digital converters for converting signals from the CCD into digital form. The digital signals are then processed, converted into analogue form, processed in analog form, and then output as the composite video signal. A digital luminance signal and either a digital composite color signal or a plurality of digital color difference signals are received as inputs into the recording section. If the digital composite color signal is received, then the signals are time-base-compressed, converted into analogue form, the composite color signal is frequency converted and filtered and the luminance signal is frequency modulated and filtered. Next, the signals are added together and recorded onto a recording medium. If the digital color difference signals are received, the digital color difference signals are multiplexed together, converted into analogue form, frequency modulated, filtered and then recorded onto one track on the recording medium. The digital luminance signal is time-base-compressed, converted into analogue form, frequency modulated, filtered, and then recorded onto a second track on the recording medium.
摘要翻译：便携式摄像机和记录装置包括摄像机部分和记录部分。摄像机部分由CCD，模数转换器组成，用于将来自CCD的信号转换为数字形式。然后数字信号被处理，转换为模拟形式，以模拟形式处理，然后作为复合视频信号输出。数字亮度信号和数字合成彩色信号或多个数字色差信号作为输入被接收到记录部分中。如果接收到数字复合彩色信号，则将信号进行时基压缩，转换为模拟形式，对彩色信号进行频率转换和滤波，并对亮度信号进行频率调制和滤波。接下来，将信号相加并记录在记录介质上。如果接收到数字色差信号，则将数字色差信号多路复用在一起，转换为模拟形式，频率调制，滤波，然后记录在记录介质上的一个磁道上。数字亮度信号被时基压缩，转换为模拟形式，频率调制，滤波，然后记录在记录介质上的第二个磁道上。

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