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1. 发明授权

US07320071B1 Secure universal serial bus 有权
标题翻译：安全通用串行总线
公开(公告)号：US07320071B1
公开(公告)日：2008-01-15
申请号：US09862986
申请日：2001-05-22
申请人： Hezi Friedman , Gadi Erlich , Ohad Falik , Daivid Briet
发明人： Hezi Friedman , Gadi Erlich , Ohad Falik , Daivid Briet
IPC分类号： G06F9/00 , G06F11/30 , H04L9/00
CPC分类号： G06F21/85
摘要： An apparatus and method for providing a secure universal serial bus (USB) is disclosed. The secure USB comprises a secure channel for transferring data. A secure USB domain device is coupled to a host computer or is embedded within a host computer. The secure USB domain device comprises a USB memory device, a USB processor, a USB host controller, and an internal USB bus coupled to each of the elements of the secure USB domain device. The elements of the secure USB domain device are not accessible by the host computer. The secure USB domain device blocks the transmission of confidential information, enables the transmission of non-confidential information, and enables the transmission of encrypted confidential information.
摘要翻译：公开了一种用于提供安全通用串行总线（USB）的设备和方法。安全USB包括用于传送数据的安全通道。安全USB域设备耦合到主计算机或嵌入在主计算机中。安全USB域设备包括耦合到安全USB域设备的每个元件的USB存储设备，USB处理器，USB主机控制器和内部USB总线。主机不能访问安全USB域设备的元素。安全USB域设备阻止机密信息的传输，实现非机密信息的传输，并且能够传输加密的机密信息。

2. 发明授权

US5446909A Binary multiplication implemented by existing hardware with minor modifications to sequentially designate bits of the operand 失效
标题翻译：由现有硬件实现的二进制乘法，稍作修改，以顺序指定操作数的位
公开(公告)号：US5446909A
公开(公告)日：1995-08-29
申请号：US989219
申请日：1992-12-11
申请人： Gideon Intrater , Ohad Falik , Aharon Ostrer , Yair Baydatch , Gadi Erlich
发明人： Gideon Intrater , Ohad Falik , Aharon Ostrer , Yair Baydatch , Gadi Erlich
IPC分类号： G06F7/53 , G06F7/52 , G06F7/523 , G06F7/72 , G06F9/302 , G06F7/50
CPC分类号： G06F7/5272 , G06F7/727 , G06F9/3001 , G06F7/49931 , G06F7/722
摘要： Binary multiplication is performed with existing data processing apparatus to which only minor modifications are required. One operand and a partial product are stored in existing latches of a CPU. The second operand is stored in a shift register which is added to the CPU. The data in the shift register is shifted from the LSB to the MSB, with a "0" being loaded into the LSB. As the bits in the first operand are designated in sequence, the value of the partial product is increased by the value in the shift register if the designated bit is a "1". After the sequencing has designated all the bits of the first operand, the partial product is taken to be the product of the multiplication.
摘要翻译：对现有的数据处理装置执行二进制乘法，仅需要稍微的修改。一个操作数和部分产品存储在CPU的现有锁存器中。第二个操作数存储在添加到CPU的移位寄存器中。移位寄存器中的数据从LSB移位到MSB，“LSB”加载。由于第一操作数中的位按顺序指定，所以如果指定位为“1”，则部分乘积的值会增加移位寄存器中的值。在排序指定了第一个操作数的所有位之后，部分乘积被认为是乘法的乘积。

3. 发明授权

US5566308A Processor core which provides a linear extension of an addressable memory space 失效
标题翻译：处理器内核提供可寻址存储空间的线性扩展
公开(公告)号：US5566308A
公开(公告)日：1996-10-15
申请号：US248769
申请日：1994-05-25
申请人： Chaim Bendelac , Dan Biran , Ohad Falik , Gadi Erlich , Jonathan Levy , Gideon Intrater
发明人： Chaim Bendelac , Dan Biran , Ohad Falik , Gadi Erlich , Jonathan Levy , Gideon Intrater
IPC分类号： G06F9/32 , G06F9/355 , G06F12/00
CPC分类号： G06F9/342 , G06F9/32 , G06F9/321
摘要： A processor core for provides a linear extension of addressable memory space of a microprocessor with minimal additional hardware and software complexity. A N+x bit pointer register (e.g. program counter) holds an N+x bit instruction address. The N+x bit instruction address provides to an execution unit a pointer to an instruction in the memory to be processed by the execution unit. An encoder encodes the N+x bit address into an N bit encoding of the N+x bit address. The processor core can thereby address 2.sup.x times more memory locations than 2.sup.N. Two other registers each hold a portion of an data address (i.e. a pointer to a datum in memory to be operated on). An address former concatenates the portions of the address in the two registers to form the data address. Therefore, the address is formed from portions of the data address stored in multiple registers without performing any arithmetic on the portions.
摘要翻译：处理器核心，用于提供微处理器的可寻址存储空间的线性扩展，同时具有最小的附加硬件和软件复杂性。 N + x位指针寄存器（例如程序计数器）保存N + x位指令地址。 N + x位指令地址向执行单元提供指向由执行单元处理的存储器中的指令的指针。编码器将N + x位地址编码为N + x位地址的N位编码。因此，处理器核可以处理比2N多两倍的存储单元。另外两个寄存器分别保存数据地址的一部分（即指向要操作的存储器中的基准的指针）。地址前缀将两个寄存器中地址的部分连接起来形成数据地址。因此，地址由存储在多个寄存器中的数据地址的部分形成，而不对这些部分执行任何算术。

4. 发明授权

US08543796B2 Optimizing performance of instructions based on sequence detection or information associated with the instructions 有权
公开(公告)号：US08543796B2
公开(公告)日：2013-09-24
申请号：US12290962
申请日：2008-11-05
申请人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
发明人： Ohad Falik , Lihu Rappoport , Ron Gabor , Yulia Kurolap , Michael Mishaeli
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F9/30032 , G06F9/30043 , G06F9/3017 , G06F9/30181 , G06F9/325 , G06F9/3855 , G06F9/3857
摘要： In one embodiment, the present invention includes an instruction decoder that can receive an incoming instruction and a path select signal and decode the incoming instruction into a first instruction code or a second instruction code responsive to the path select signal. The two different instruction codes, both representing the same incoming instruction may be used by an execution unit to perform an operation optimized for different data lengths. Other embodiments are described and claimed.

5. 发明申请

US20130132636A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130132636A1
公开(公告)日：2013-05-23
申请号：US13690931
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/42
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

6. 发明申请

US20130091317A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 审中-公开
公开(公告)号：US20130091317A1
公开(公告)日：2013-04-11
申请号：US13691016
申请日：2012-11-30
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David J. Harriman , Mark B. Rosenbluth , Ajay V. Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert G. Blankenship , Ohad Falik , Avi Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/40
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.

7. 发明申请

US20110208925A1 PCI EXPRESS ENHANCEMENTS AND EXTENSIONS 有权
标题翻译： PCI EXPRESS增强和扩展
公开(公告)号：US20110208925A1
公开(公告)日：2011-08-25
申请号：US12861439
申请日：2010-08-23
申请人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
发明人： Jasmin Ajanovic , Mahesh Wagh , Prashant Sethi , Debendra Das Sharma , David Harriman , Mark Rosenbluth , Ajay Bhatt , Peter Barry , Scott Dion Rodgers , Anil Vasudevan , Sridhar Muthrasanallur , James Akiyama , Robert Blankenship , Ohad Falik , Avi (Abraham) Mendelson , Ilan Pardo , Eran Tamari , Eliezer Weissmann , Doron Shamia
IPC分类号： G06F13/14 , G06F12/00
CPC分类号： G06F12/0831 , G06F1/3203 , G06F1/324 , G06F1/3253 , G06F12/0815 , G06F13/385 , G06F13/4045 , G06F13/4068 , G06F13/4265 , G06F2212/621 , H04L12/66 , Y02D10/126 , Y02D10/151
摘要： A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Message codes for atomic operations to arbitrate ownership between system devices/resources are included to allow efficient access/ownership of shared data. Loose transaction ordering provided for while maintaining corresponding transaction priority to memory locations to ensure data integrity and efficient memory access. Active power sub-states and setting thereof is included to allow for more efficient power management. And, caching of device local memory in a host address space, as well as caching of system memory in a device local memory address space is provided for to improve bandwidth and latency for memory accesses.
摘要翻译：这里描述了用于增强/扩展串行点对点互连架构的方法和装置，例如外围组件互连Express（PCIe）。提供了时间和地点缓存提示和预取提示，以改进系统范围的缓存和预取。包括用于仲裁系统设备/资源之间的所有权的原子操作的消息代码，以便有效地访问/拥有共享数据。提供的松散的事务排序，同时将对应的事务优先级保持到内存位置，以确保数据完整性和高效的内存访问。包括有功功率子状态及其设置以允许更有效的电源管理。并且，提供设备本地存储器在主机地址空间中的缓存以及设备本地存储器地址空间中的系统存储器的缓存，以提高存储器访问的带宽和延迟。

8. 发明授权

US07865646B1 Sharing of functions between an embedded controller and a host processor 有权
标题翻译：共享嵌入式控制器和主机处理器之间的功能
公开(公告)号：US07865646B1
公开(公告)日：2011-01-04
申请号：US11490008
申请日：2006-07-20
申请人： Ohad Falik , Yehezkel Friedman , Victor Flachs , Yuval Kirschner
发明人： Ohad Falik , Yehezkel Friedman , Victor Flachs , Yuval Kirschner
IPC分类号： G06F12/00
CPC分类号： G06F13/387
摘要： An improved system is described for allowing an embedded controller and a host processor to share access to modules in a computer system. The shared access system of the present invention enables exclusive, one-at-a-time access by a processor to a module and concurrent access by more than one processor to a module. An internal bus with two power sources is used to allow continued access by one of the processors when one of the two power sources is not providing power. Asynchronous clocking is provided to allow increased throughput to modules. An example of a protocol that allows an embedded controller to access more than one module is also described.
摘要翻译：描述了一种改进的系统，用于允许嵌入式控制器和主处理器共享对计算机系统中的模块的访问。本发明的共享访问系统使得处理器能够对模块进行一次性一次访问，并且由多个处理器对模块的并发访问。当两个电源之一不提供电源时，使用具有两个电源的内部总线来允许其中一个处理器继续访问。提供异步时钟以允许增加模块的吞吐量。还描述了允许嵌入式控制器访问多于一个模块的协议的示例。

9. 发明授权

US07680966B1 Memory interface including generation of timing signals for memory operation 有权
标题翻译：存储器接口包括产生用于存储器操作的定时信号
公开(公告)号：US07680966B1
公开(公告)日：2010-03-16
申请号：US10933697
申请日：2004-09-03
申请人： Ohad Falik , Paul Johnston
发明人： Ohad Falik , Paul Johnston
IPC分类号： G06F3/00
CPC分类号： G11C5/02 , H01L24/05 , H01L25/0657 , H01L2224/48145 , H01L2224/49171 , H01L2225/06562 , H01L2924/01087 , H01L2924/14 , H01L2924/19043 , H01L2924/3011 , H01L2924/00012
摘要： A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any within a given range of frequencies. A frequency value signal conveying the value of the frequency of the clock signal is also transmitted. The interface controller includes circuitry for deriving from the clock signal and from the frequency value signal at least one timing signal for any operation in the memory device.
摘要翻译：存储器件包括用于通过通信链路与半导体器件通信的接口控制器。时钟信号通过链路从半导体器件发送到存储器件。时钟信号的频率可以在给定的频率范围内的任何频率。传送时钟信号的频率值的频率值信号也被发送。接口控制器包括用于从时钟信号和频率值信号导出用于存储器件中的任何操作的至少一个定时信号的电路。

10. 发明申请

US20090006765A1 METHOD AND SYSTEM FOR REDUCING CACHE CONFLICTS 有权
标题翻译：减少缓存冲突的方法和系统
公开(公告)号：US20090006765A1
公开(公告)日：2009-01-01
申请号：US11770107
申请日：2007-06-28
申请人： Ben-Zion Friedman , Ohad Falik
发明人： Ben-Zion Friedman , Ohad Falik
IPC分类号： G06F12/00
CPC分类号： H04L49/9047 , H04L49/90 , H04L49/901
摘要： Disclosed is a system and method for storing a plurality of data packets in a plurality of memory buffers in a cache memory for reducing cache conflicts. The method includes determining size of each of a plurality of data packets; storing a first data packet of the plurality of data packets starting from a first address in a first memory buffer of the plurality of memory buffers; determining an offset based on the size of the first data packet; and storing a second data packet in a second buffer starting from a second address based on the offset.
摘要翻译：公开了一种用于将多个数据分组存储在高速缓冲存储器中的多个存储器缓冲器中用于减少高速缓存冲突的系统和方法。该方法包括确定多个数据分组中的每一个的大小; 从所述多个存储器缓冲器的第一存储器缓冲器中的第一地址开始存储所述多个数据分组的第一数据分组; 基于所述第一数据分组的大小确定偏移量; 以及基于所述偏移从第二地址开始将第二数据分组存储在第二缓冲器中。

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