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    • 2. 发明授权
    • Nanopore based ion-selective electrodes
    • 基于纳米孔的离子选择性电极
    • US08123922B2
    • 2012-02-28
    • US11852061
    • 2007-09-07
    • Henry S. WhiteRyan J. WhiteRichard B. BrownHakhyun NamJun Ho Shim
    • Henry S. WhiteRyan J. WhiteRichard B. BrownHakhyun NamJun Ho Shim
    • G01N27/333
    • G01N27/333Y10T156/10
    • Nanopore based ion-selective electrodes and methods of their manufacture as well as methods for their use are disclosed and described. The nanopore based ion-selective electrode can include a pore being present in a solid material and having a nanosize opening in the solid material, a metal conductor disposed inside the pore opposite the opening in the solid material, a reference electrode material contacting said metal conductor and disposed inside the pore, a conductive composition in contact with the reference electrode and disposed in the pore, and an ion-selective membrane. The ion-selective membrane can be configured to isolate the metal conductor, reference electrode material, and conductive composition together within the pore.
    • 公开和描述了基于纳米孔的离子选择性电极及其制造方法及其使用方法。 基于纳米孔的离子选择性电极可以包括存在于固体材料中并在固体材料中具有纳米尺寸开口的孔,设置在与固体材料中的开口相对的孔内的金属导体,与金属导体接触的参考电极材料 并且设置在孔内,与参考电极接触并设置在孔中的导电组合物和离子选择性膜。 离子选择性膜可以被配置为在孔内将金属导体,参比电极材料和导电组合物隔离在一起。
    • 3. 发明授权
    • Linearizing apparatus and method
    • 线性化装置和方法
    • US07132874B2
    • 2006-11-07
    • US10829575
    • 2004-04-22
    • Michael S. McCorquodaleRichard B. BrownMei Kim Ding
    • Michael S. McCorquodaleRichard B. BrownMei Kim Ding
    • G06F7/556
    • G06G7/122
    • An apparatus and method are disclosed which provide a substantially linear relationship between an input signal, such as an input voltage or current, and a predetermined parameter, such as a frequency response or capacitance of a parallel plate capacitor or varactor. The apparatus comprises a square root converter and a logarithmic generator. The square root converter is adapted to provide a square root signal which is substantially proportional to a square root of the input signal. In the various embodiments, the logarithmic generator is adapted to provide an applied signal which is substantially proportional to a sum of a logarithm of the input signal plus the square root of the input signal. The applied signal is a pre-distorted signal which generally has a non-linear relation to the predetermined parameter and which, when applied, allows the predetermined parameter to vary substantially linearly with the input signal.
    • 公开了一种在输入信号(例如输入电压或电流)与预定参数(诸如平行板电容器或变容二极管的频率响应或电容)之间提供基本线性关系的装置和方法。 该装置包括平方根转换器和对数发生器。 平方根转换器适于提供与输入信号的平方根成正比的平方根信号。 在各种实施例中,对数发生器适于提供基本上与输入信号的对数加上输入信号的平方根的和成正比的施加信号。 施加的信号是预失真信号,其通常与预定参数具有非线性关系,并且当被施加时,允许预定参数与输入信号基本上线性地变化。
    • 4. 发明授权
    • Ultra high frequency ring oscillator with voltage controlled frequency capabilities
    • 具有电压控制频率功能的超高频环形振荡器
    • US07113048B2
    • 2006-09-26
    • US10988463
    • 2004-11-12
    • Richard B. BrownGary D. CarpenterFadi H. Gebara
    • Richard B. BrownGary D. CarpenterFadi H. Gebara
    • H03B5/24H03K3/03H03L7/099
    • H03K3/0315H03K3/356139H03K5/133H03L7/0995
    • A pseudo Set/Reset latch circuit is configured with modified NOR or NAND gates wherein one of the series pull-up devices or pull-down devices is removed. A minimum of three pseudo Set/Reset latches may be coupled as a ring oscillator generating an output and a non-skewed complementary output. Additionally, feed-forward inverting stages may be coupled in parallel with inverting paths in the ring oscillator primary path to further increase the frequency range of the ring oscillator. The pseudo Set/Reset latch circuits and the feed-forward inverting stages may be configured with voltage controlled devices that alter the delay of the stages as a means for varying the frequency of the ring oscillator either by varying the current drive of the circuitry driving the output of the latch stages or by varying the conductance of devices coupling between the latch stages. Feedforward inverting stages may comprise pseudo latches or inverter gates.
    • 伪置位/复位锁存电路配置有修改的NOR或NAND门,其中串联上拉器件或下拉器件中的一个被去除。 可以将至少三个伪设置/复位锁存器耦合作为产生输出和非偏斜互补输出的环形振荡器。 此外,前馈反相级可以与环形振荡器主路径中的反相路径并联耦合,以进一步增加环形振荡器的频率范围。 伪设置/复位锁存电路和前馈反相级可以配置有电压控制的装置,其通过改变驱动电路的电路的电流驱动来改变级的延迟,作为改变环形振荡器的频率的手段 锁存级的输出或通过改变耦合在锁存级之间的器件的电导。 前馈反相级可以包括伪锁存器或反相器门。
    • 5. 发明授权
    • Solid state ion sensor with silicon membrane
    • 具有硅膜的固态离子传感器
    • US5102526A
    • 1992-04-07
    • US517636
    • 1990-05-02
    • Richard B. BrownGeun-Sig Cha
    • Richard B. BrownGeun-Sig Cha
    • G01N27/327G01N27/333G01N27/414
    • G01N27/333
    • A silicone matrix is employed to form a substance-sensitive membrane which is particularly suited for installation on a solid state sensor. The ionophore may be a potassium ionophore, an ammonium ionophore or any other ionophore. The membrane may be coupled to the molecule of interest through a bioactive agent, such as an enzyme, an immunochemical, bacteria, antibody, virus, or antigen. The resulting substance-sensitive membrane has electrochemical properties which compare favorably to those of conventional PVC membranes, and exhibit significantly greater adhesion to glasses and semiconductor substrate materials. The improved adhesion will prolong the life of the sensors and prevent the formation of electrolyte shunts which have been known to render solid state sensors inoperative.
    • 使用有机硅基体形成特别适合于安装在固态传感器上的物质敏感膜。 离子载体可以是钾离子载体,铵离子载体或任何其它离子载体。 膜可以通过生物活性剂(例如酶,免疫化学,细菌,抗体,病毒或抗原)与感兴趣的分子偶联。 所得到的物质敏感膜具有与常规PVC膜相当的电化学性能,并且对玻璃和半导体衬底材料表现出显着更大的粘合性。 改善的粘合力将延长传感器的使用寿命,并防止已知使固态传感器不起作用的电解液分流器的形成。
    • 6. 发明授权
    • Method of reducing leakage current in sub one volt SOI circuits
    • 降低亚一伏SOI电路漏电流的方法
    • US06952113B2
    • 2005-10-04
    • US10644211
    • 2003-08-20
    • Richard B. BrownChing-Te K. ChuangPeter W. CookKoushik K. DasRajiv V. Joshi
    • Richard B. BrownChing-Te K. ChuangPeter W. CookKoushik K. DasRajiv V. Joshi
    • H03K19/00A03K19/003
    • H03K19/0016
    • A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETs) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.
    • 具有降低的亚阈值泄漏的多阈值集成电路(IC)和减少泄漏的方法。 电路逻辑电路和电源连接(V SUB)和GND之间的可选供电开关器件(NFET和/或PFET)的电路具有比正常电路器件更高的阈值。 当供电开关装置打开时,一些装置可能具有降低的阈值。 具有更高阈值电压和宽度的标题/页脚装置可用于进一步降低电阻和保持/降低电阻。 或者,可以堆叠高阈值装置以进一步将泄漏减少到达到甚至更高阈值所达到的点。 中间电源连接在器件上可能具有去耦电容,器件可以锥形化,以获得最佳堆叠高度和最佳锥度比,以最大限度地减少电路泄漏和电路延迟。