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1. 发明授权

US08078998B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08078998B2
公开(公告)日：2011-12-13
申请号：US12839750
申请日：2010-07-20
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： G06F17/50
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

2. 发明申请

US20090079005A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20090079005A1
公开(公告)日：2009-03-26
申请号：US11860955
申请日：2007-09-25
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L29/76 , B44C1/22 , G06F17/50 , H01L21/3205 , H01L21/76
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

3. 发明授权

US07785946B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US07785946B2
公开(公告)日：2010-08-31
申请号：US11860955
申请日：2007-09-25
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L21/338
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

4. 发明授权

US08809958B2 Integrated circuits and methods of design and manufacture thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US08809958B2
公开(公告)日：2014-08-19
申请号：US13296578
申请日：2011-11-15
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/06
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

5. 发明申请

US20120074499A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20120074499A1
公开(公告)日：2012-03-29
申请号：US13296578
申请日：2011-11-15
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/08 , G03F1/38 , G03F1/48 , G06F17/50 , G03F1/00
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

6. 发明申请

US20100276759A1 Integrated Circuits and Methods of Design and Manufacture Thereof 有权
标题翻译：集成电路及其设计和制造方法
公开(公告)号：US20100276759A1
公开(公告)日：2010-11-04
申请号：US12839750
申请日：2010-07-20
申请人： Henning Haffner , Manfred Eller , Richard Lindsay
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： H01L27/088 , H01L27/02 , G06F17/50 , H01L21/64
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.
摘要翻译：公开了集成电路及其制造和设计方法。例如，制造方法包括使用第一掩模对形成多个第一和第二特征的栅极材料进行图案化。第一特征形成半导体器件的栅电极，而第二特征是虚拟电极。基于这些虚拟电极的位置，使用第二掩模去除所选择的虚拟电极。该方法的使用提供了更大的灵活性，为不同的目标定制单个设备。

7. 发明申请

US20090042359A1 Structure and Method of Producing Isolation with Non-Dopant Implantation 有权
标题翻译：用非掺杂植入法分离生产的结构和方法
公开(公告)号：US20090042359A1
公开(公告)日：2009-02-12
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/71 , H01L29/00
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

8. 发明授权

US08431972B2 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US08431972B2
公开(公告)日：2013-04-30
申请号：US11638067
申请日：2006-12-13
申请人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
发明人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
IPC分类号： H01L29/66
CPC分类号： H01L21/26513 , H01L27/027 , H01L29/0619 , H01L29/665 , H01L29/7833
摘要： An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.
摘要翻译： ESD保护器件包括半导体本体，形成在半导体本体中的沟道上的栅极，该沟道掺杂有第一导电类型的掺杂剂的第一浓度。第一源极/漏极区域形成在与栅极的第一边缘相邻的半导体本体的表面上，其中第一源极/漏极区域掺杂有与第一导电类型相反的第二导电类型的掺杂物，并且至少第一源/漏区的一部分掺杂有第一导电类型的掺杂剂。第二导电型掺杂物的浓度超过第一导电型掺杂剂的浓度，并且第一源极/漏极中的第一导电类型掺杂剂的浓度超过第一浓度。第二源极/漏极区域还形成在与栅极的第二边缘相邻的半导体本体的上表面处，其中第二源极/漏极区域掺杂有第二导电类型的掺杂物。

9. 发明授权

US07737009B2 Method of implanting a non-dopant atom into a semiconductor device 有权
标题翻译：将非掺杂剂原子注入到半导体器件中的方法
公开(公告)号：US07737009B2
公开(公告)日：2010-06-15
申请号：US11836008
申请日：2007-08-08
申请人： Richard Lindsay , Yong Meng Lee , Manfred Eller
发明人： Richard Lindsay , Yong Meng Lee , Manfred Eller
IPC分类号： H01L21/265
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/26566 , H01L21/2658 , H01L21/26586 , H01L21/76237 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method of forming an isolation trench structure is disclosed, the method includes forming an isolation trench in a semiconductor body associated with an isolation region, and implanting a non-dopant atom into the isolation trench, thereby forming a region to modify the halo profile in the semiconductor body. Subsequently, the isolation trench is filled with a dielectric material.
摘要翻译：公开了一种形成隔离沟槽结构的方法，该方法包括在与隔离区相关联的半导体本体中形成隔离沟槽，并将非掺杂剂原子注入到隔离沟槽中，从而形成一个区域以修改光刻轮廓半导体体。随后，隔离沟槽填充有电介质材料。

10. 发明申请

US20080142849A1 Semiconductor ESD device and method of making same 有权
标题翻译：半导体ESD器件及其制造方法
公开(公告)号：US20080142849A1
公开(公告)日：2008-06-19
申请号：US11638067
申请日：2006-12-13
申请人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
发明人： David Alvarez , Richard Lindsay , Manfred Eller , Cornelius Christian Russ
IPC分类号： H01L29/76
CPC分类号： H01L21/26513 , H01L27/027 , H01L29/0619 , H01L29/665 , H01L29/7833
摘要： An ESD protection device includes a semiconductor body, a gate formed over a channel in the semiconductor body, the channel being doped with a first concentration of dopants of a first conductivity type. A first source/drain region is formed on the surface of the semiconductor body adjacent to a first edge of the gate, wherein the first source/drain region is doped with a dopant of a second conductivity type opposite the first conductivity type, and at least a portion of the first source/drain region is doped with a dopant of the first conductivity type. The concentration of the second conductivity type dopant exceeds the concentration of the first conductivity type dopant, and the concentration of the first conductivity type dopant in the first source/drain exceeds the first concentration. A second source/drain region is also formed at the upper surface of the semiconductor body adjacent to a second edge of the gate, wherein the second source/drain region is doped with a dopant of the second conductivity type.
摘要翻译： ESD保护器件包括半导体本体，形成在半导体本体中的沟道上的栅极，该沟道掺杂有第一导电类型的掺杂剂的第一浓度。第一源极/漏极区域形成在与栅极的第一边缘相邻的半导体本体的表面上，其中第一源极/漏极区域掺杂有与第一导电类型相反的第二导电类型的掺杂物，并且至少第一源/漏区的一部分掺杂有第一导电类型的掺杂剂。第二导电型掺杂物的浓度超过第一导电型掺杂剂的浓度，并且第一源极/漏极中的第一导电类型掺杂剂的浓度超过第一浓度。第二源极/漏极区域还形成在与栅极的第二边缘相邻的半导体本体的上表面处，其中第二源极/漏极区域掺杂有第二导电类型的掺杂物。

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