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1. 发明授权

US06983356B2 High performance memory device-state aware chipset prefetcher 失效
标题翻译：高性能存储器件状态感知芯片组预取器
公开(公告)号：US06983356B2
公开(公告)日：2006-01-03
申请号：US10325795
申请日：2002-12-19
申请人： Hemant G. Rotithor , Randy B. Osborne , Donald W. McCauley
发明人： Hemant G. Rotithor , Randy B. Osborne , Donald W. McCauley
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F2212/502 , G06F2212/6022
摘要： A method of prefetching from a memory device includes determining a prefetch buffer hit rate (PBHR) and a memory bandwidth utilization (MBU) rate. Prefetches are inserted aggressively if the memory bandwidth utilization (MBU) rate is above a MBU threshold level and the prefetch buffer hit rate (PBHR) is above a PBHR threshold level. Prefetches are inserted conservatively if the memory bandwidth utilization (MBU) rate is above the MBU threshold level and the prefetch buffer hit rate (PBHR) is below the PBHR threshold level.
摘要翻译：从存储器件预取的方法包括确定预取缓冲器命中率（PBHR）和存储器带宽利用率（MBU）速率。如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）高于PBHR阈值级别，则会大大插入预取。如果存储器带宽占用率（MBU）高于MBU阈值级别，并且预取缓冲区命中率（PBHR）低于PBHR阈值级别，则保留预存取值。

2. 发明授权

US07127574B2 Method and apparatus for out of order memory scheduling 失效
标题翻译：无序存储器调度的方法和装置
公开(公告)号：US07127574B2
公开(公告)日：2006-10-24
申请号：US10692245
申请日：2003-10-22
申请人： Hemant G. Rotithor , Randy B. Osborne , Nagi Aboulenein
发明人： Hemant G. Rotithor , Randy B. Osborne , Nagi Aboulenein
IPC分类号： G06F12/02
CPC分类号： G06F13/1631
摘要： Embodiments of the present invention provide an algorithm for scheduling read and write transactions to memory out of order to improve command and data bus utilization and gain performance over a range of workloads. In particular, memory transactions are sorted into queues so that they do not have page conflict with each other and are scheduled from these queues out of order in accordance with read and write scheduling algorithms to optimize latency.
摘要翻译：本发明的实施例提供了一种用于将读取和写入事务调度到存储器的算法，以改进命令和数据总线利用率并在一系列工作负载上获得性能的算法。特别地，存储器事务被排序成队列，使得它们不具有彼此的页冲突，并且根据读和写调度算法从这些队列排序排序以优化等待时间。

3. 发明授权

US07350030B2 High performance chipset prefetcher for interleaved channels 有权
标题翻译：用于交错通道的高性能芯片组预取器
公开(公告)号：US07350030B2
公开(公告)日：2008-03-25
申请号：US11172401
申请日：2005-06-29
申请人： Hemant G. Rotithor , Abhishek Singhal , Randy B. Osborne , Zohar Bogin , Raul N. Gutierrez , Buderya S. Acharya , Surya Kareenahalli
发明人： Hemant G. Rotithor , Abhishek Singhal , Randy B. Osborne , Zohar Bogin , Raul N. Gutierrez , Buderya S. Acharya , Surya Kareenahalli
IPC分类号： G06F12/00 , G06F9/00
CPC分类号： G06F12/0862 , G06F12/0215 , G06F12/0607 , G06F2212/6022 , G06F2212/6026
摘要： The invention comprises an apparatus and method of prefetching from a memory device having interleaved channels. The chipset prefetcher comprises a stride detector to detect a stride in a stream, a prefetch injector to insert prefetches onto the memory device, a channel mapper to map the prefetches to each channel of the memory device, a scheduler to schedule the prefetches onto the memory device in a DRAM-state aware manner, a throttling heuristic to scale the number of prefetches, and a prefetch data buffer to store prefetch data. The method of prefetching comprises tracking the state of streams, detecting a stride on one of the streams, selecting the stream with the stride for prefetch injection, enqueueing prefetches from the selected stream, mapping the prefetches to each of the interleaved channels, injecting the prefetches from the selected stream into each of the interleaved channels, and scheduling the prefetches onto the memory device in a DRAM-state aware manner.
摘要翻译：本发明包括一种从具有交织信道的存储装置预取的装置和方法。芯片组预取器包括用于检测流中的步幅的步幅检测器，用于将预取插入存储器件的预取注入器，用于将预取映射到存储器件的每个通道的通道映射器，调度器以将预取计划到存储器上 DRAM状态感知方式的设备，限制预取数量的限制启发式，以及预取数据缓冲器来存储预取数据。预取方法包括跟踪流的状态，检测一条流上的步幅，选择用于预取注入的步幅的流，从所选择的流中引入预取，将预取映射到每个交错通道，注入预取从所选择的流到每个交织的信道，并且以DRAM状态感知的方式将预取调度到存储器设备上。

4. 发明授权

US07167947B2 Memory post-write page closing apparatus and method 有权
标题翻译：内存后写入页面关闭装置和方法
公开(公告)号：US07167947B2
公开(公告)日：2007-01-23
申请号：US10801201
申请日：2004-03-15
申请人： Hemant G. Rotithor , Randy B. Osborne
发明人： Hemant G. Rotithor , Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G06F12/0215 , G06F13/1673
摘要： Apparatus and method to select write transactions and to selectively mark a write transaction with a page closing hint to cause the page in a memory device to which the write transaction is directed to be closed immediately after the write transaction is carried out if no other write transaction is found in a buffer of pending write transactions that is directed to the same rank, bank and page to minimize incidents of incurring lengthy page miss delays.
摘要翻译：选择写事务的装置和方法，以及如果没有其他写事务，则在执行写事务之后，使用页关闭提示来选择性地标记写事务，以使得在写事务被定向到的存储器设备中的页被立即关闭在等待写入交易的缓冲区中找到，该缓冲区被定向到相同的等级，银行和页面，以最小化发生长时间的页面错误延迟的事件。

5. 发明授权

US07386658B2 Memory post-write page closing apparatus and method 有权
标题翻译：内存后写入页面关闭装置和方法
公开(公告)号：US07386658B2
公开(公告)日：2008-06-10
申请号：US10877356
申请日：2004-06-25
申请人： Hemant G. Rotithor , Randy B. Osborne
发明人： Hemant G. Rotithor , Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G06F13/1668 , G06F12/0215 , G06F12/0607 , G06F12/0804 , G11C15/00
摘要： Apparatus and method to receive new requests for write transactions; compare rank, bank and page of new requests to those already stored and assemble chains of write commands directed to the same rank, bank and page; select and transmit write commands from one chain at a time until each chain is done; and select a next chain of write commands to transmit, while creating and using a write page closing hint to determine when a change between pages of a given rank and bank should bring about the preemptive closing of a page to minimize incidents of incurring lengthy page miss delays.
摘要翻译：接收新的写事务请求的装置和方法; 将已经存储的订单，新请求的页面和页面与对同一等级，银行和页面的写入命令的组合链进行比较; 一次从一个链中选择和发送写入命令，直到每个链完成; 并选择下一个写入命令链以传输，同时创建和使用写入页面关闭提示来确定给定等级和银行的页面之间的更改是否应该引起页面的抢占关闭，以最大限度地减少发生冗长页面错误的事件延误

6. 发明授权

US09087603B2 Method and apparatus for selective DRAM precharge 有权
公开(公告)号：US09087603B2
公开(公告)日：2015-07-21
申请号：US12369105
申请日：2009-02-11
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G11C8/00 , G11C11/4094 , G11C7/10 , G11C8/18
CPC分类号： G11C11/4094 , G11C7/1012 , G11C8/18
摘要： Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.

7. 发明授权

US07673111B2 Memory system with both single and consolidated commands 有权
标题翻译：具有单一和统一命令的内存系统
公开(公告)号：US07673111B2
公开(公告)日：2010-03-02
申请号：US11318028
申请日：2005-12-23
申请人： Shelley Chen , Randy B. Osborne
发明人： Shelley Chen , Randy B. Osborne
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/1642 , Y02D10/14
摘要： In some embodiments, a chip includes a request queue to include write requests, and scheduling circuitry to schedule commands including commands in response to the write requests. The chip also includes mode selection circuitry to monitor the request queue and in response thereto to select a first or a second mode for the scheduling circuitry, wherein in the first mode the scheduling circuitry schedules certain commands as separate single commands and in the second mode the scheduling circuitry schedules consolidated commands to represent more than one separate single command. Other embodiments are described.
摘要翻译：在一些实施例中，芯片包括包括写入请求的请求队列，以及调度电路来调度包括响应于写入请求的命令的命令。芯片还包括模式选择电路，用于监视请求队列并响应于此选择用于调度电路的第一或第二模式，其中在第一模式中，调度电路将某些命令调度为单独的单个命令，并且在第二模式中调度电路安排统一的命令来表示多个独立的单个命令。描述其他实施例。

8. 发明授权

US07167946B2 Method and apparatus for implicit DRAM precharge 有权
标题翻译：隐式DRAM预充电的方法和装置
公开(公告)号：US07167946B2
公开(公告)日：2007-01-23
申请号：US10676882
申请日：2003-09-30
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G06F12/00
CPC分类号： G11C11/4094 , G11C11/4076
摘要： Apparatus and method to implicitly transmit a command to close a row of memory cells within a memory device as part of the transmission of an activate command to open another row of memory cells within the memory device.
摘要翻译：用于隐藏地发送命令以关闭存储器设备内的一行存储器单元的装置和方法，作为激活命令的传输的一部分，以打开存储器设备内的另一行存储器单元。

9. 发明授权

US06941425B2 Method and apparatus for read launch optimizations in memory interconnect 有权
标题翻译：存储器互连中读取启动优化的方法和装置
公开(公告)号：US06941425B2
公开(公告)日：2005-09-06
申请号：US10010994
申请日：2001-11-12
申请人： Randy B. Osborne
发明人： Randy B. Osborne
IPC分类号： G06F13/16 , G06F13/00
CPC分类号： G06F13/1626 , G06F13/161
摘要： A method and apparatus for the optimization of memory read operations via read launch optimizations in memory interconnect are disclosed. In one embodiment, a write request may be preempted by a read request.
摘要翻译：公开了一种通过存储器互连中的读取启动优化优化存储器读取操作的方法和装置。在一个实施例中，写请求可以被读请求抢占。

10. 发明授权

US6008813A Real-time PC based volume rendering system 失效
标题翻译：实时基于PC的音量渲染系统
公开(公告)号：US6008813A
公开(公告)日：1999-12-28
申请号：US905238
申请日：1997-08-01
申请人： Hugh C. Lauer , Randy B. Osborne , Hanspeter Pfister
发明人： Hugh C. Lauer , Randy B. Osborne , Hanspeter Pfister
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00 , G06T15/08 , G06T15/40
CPC分类号： G06T15/08 , G06T1/60 , G06T15/005 , G06T15/40
摘要： Apparatus is provided to enable real-time volume rendering on a personal computer or a desktop computer in which a technique involving blocking of voxel data organizes the data so that all voxels within a block are stored at consecutive memory addresses within a single memory model, making possible fetching an entire block of data in a burst rather than one voxel at a time. This permits utilization of DRAM memory modules which provide high capacity and low cost with substantial space savings. Additional techniques including sectioning reduces the amount of intermediate storage in a processing pipeline to an acceptable level for semiconductor implementation. A multiplexing technique takes advantage of blocking to reduce the amount of data needed to be transmitted per block, thus reducing the number of pins and the rates at which data must be transmitted across the pins connecting adjacent processing modules with each other. A mini-blocking technique saves the time needed to process sections by avoiding reading entire blocks for voxels near the boundary between a section and previously processed sections.
摘要翻译：提供了一种用于在个人计算机或台式计算机上实时体积渲染的装置，其中涉及阻塞体素数据的技术组织数据，使得块内的所有体素被存储在单个存储器模型内的连续存储器地址处，使得一次可能在突发而不是一个体素中获取整个数据块。这允许利用提供高容量和低成本的DRAM存储器模块，同时节省了大量空间。包括切片的其他技术将处理管线中的中间存储量减少到半导体实现的可接受水平。复用技术利用阻塞来减少每个块需要传输的数据量，从而减少引脚数量和数据必须在连接相邻处理模块的引脚之间传输的速率。微型阻塞技术通过避免读取部分和先前处理的部分之间边界附近的体素的整个块来节省处理部分所需的时间。

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