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1. 发明授权

US07675930B2 Chip circuit for combined and data compressed FIFO arbitration for a non-blocking switch 失效
标题翻译：用于非阻塞开关的组合和数据压缩FIFO仲裁的片状电路
公开(公告)号：US07675930B2
公开(公告)日：2010-03-09
申请号：US12033867
申请日：2008-02-19
申请人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
发明人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
IPC分类号： H04L12/54
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A system for switching data packets through a multiple (m) input, multiple (n) output switching device providing switching having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译：一种用于通过多输入（n）输出切换装置切换数据分组的系统，其提供具有快速单周期吞吐量的切换。相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

2. 发明授权

US5321706A Method and apparatus for checking the address and contents of a memory array 失效
标题翻译：用于检查存储器阵列的地址和内容的方法和装置
公开(公告)号：US5321706A
公开(公告)日：1994-06-14
申请号：US719456
申请日：1991-06-24
申请人： Ingemar Holm , Helmut Kohler , Peter Mannherz , Norbert Schumacher , Gerhard Zilles
发明人： Ingemar Holm , Helmut Kohler , Peter Mannherz , Norbert Schumacher , Gerhard Zilles
IPC分类号： G06F12/16 , G06F11/10 , G06F11/00
CPC分类号： G06F11/1016 , G06F2201/88
摘要： A circuit for checking the memory array address and contents is described. The circuit consists of at least one write address counter (120) and at least one read address counter (130). Before a data word is read into the array, each of its check bits are XORed with one bit of the address location at which the word is to be written. On reading out the word, the check bits are again XORed with the bits of the address location to restore their original value and the parity of the data word is checked. If the parity is found to be incorrect then it is known that an error has occurred either on reading in or reading out and the appropriate action can be taken.
摘要翻译：描述用于检查存储器阵列地址和内容的电路。电路由至少一个写地址计数器（120）和至少一个读地址计数器（130）组成。在将数据字读入阵列之前，其每个校验位与要写入该字的地址位置的一位进行异或运算。在读出该字时，校验位将再次与地址位置的位进行异或，以恢复其原始值，并检查数据字的奇偶校验。如果发现奇偶校验是不正确的，则知道在读入或读出时发生错误，并且可以采取适当的操作。

3. 发明授权

US07107490B2 IML-stream generated error insertion / FRU isolation 失效
标题翻译： IML流生成错误插入/ FRU隔离
公开(公告)号：US07107490B2
公开(公告)日：2006-09-12
申请号：US10313326
申请日：2002-12-06
申请人： Andreas Eisenhoffer , Harald Fischer , Helmut Kohler , Norbert Schumacher
发明人： Andreas Eisenhoffer , Harald Fischer , Helmut Kohler , Norbert Schumacher
IPC分类号： G06F11/00
CPC分类号： G06F11/261
摘要： The present invention relates to a method and system for testing error detection programs dedicated for detecting hardware failures in a computer system, in which error case patterns comprising stimuli values are generated and response patterns to the hardware are evaluated. In order to develop and debug such error detection programs already at an early phase during hardware development it is proposed to feed a simulation model (26) of said hardware with said error patterns, and after running said model, evaluating (12) the model response patterns generated by the simulation model and comparing the response patterns with those expected as a result of the error detection program.
摘要翻译：本发明涉及用于检测专用于检测计算机系统中的硬件故障的错误检测程序的方法和系统，其中产生包括刺激值的错误情况模式并评估对硬件的响应模式。为了在硬件开发过程中早期阶段开发和调试这种错误检测程序，建议用所述错误模式来提供所述硬件的仿真模型（26），并且在运行所述模型之后，评估（12）模型响应仿真模型生成的模式，并将响应模式与错误检测程序的结果进行比较。

4. 发明授权

US5694400A Checking data integrity in buffered data transmission 失效
标题翻译：检查缓冲数据传输中的数据完整性
公开(公告)号：US5694400A
公开(公告)日：1997-12-02
申请号：US433410
申请日：1995-08-10
申请人： Gilles Gervais , Ingemar Holm , Helmut Kohler , Thomas Koehler , Norbert Schumacher , Gerhard Zilles
发明人： Gilles Gervais , Ingemar Holm , Helmut Kohler , Thomas Koehler , Norbert Schumacher , Gerhard Zilles
IPC分类号： G06F7/00 , G06F11/00 , G06F11/10 , G06F11/16 , G11C29/10 , G11C29/24
CPC分类号： G06F11/1008 , G06F11/0763 , G11C29/10 , G11C29/24 , G06F7/00
摘要： Discloses a device and a method for checking by means of a checker (100). the data incorporating check bits read into a memory stack. The device comprises a first counter (20), which is connected through logical gates (30a-d) with some of the memory input lines (25), and a second counter (80) between the checker (100) and the memory (50), which is connected through logical gates (70a-d) to the memory output lines (55) corresponding to the memory input lines (25) with the first (20) and the second (80). counters generating continuous binary values. The method comprising the following stages: combination of the data to be read in with a value generated by a first counter (20) in accordance with an exclusive-OR operation; reading the logically combined data into the memory (50); reading the logically combined data from the memory (50); combination of the logically combined data read out with a value generated by a second counter (80) in accordance with an exclusive-OR operation; checking the data read out for parity in a parity checker (100). The invention may be used in a buffer memory (50) between two asynchronously timed buses.
摘要翻译： PCT No.PCT / EP93 / 03572 Sec。 371日期：1995年8月10日 102（e）日期1995年8月10日PCT提交1993年12月15日PCT公布。公开号WO94 / 15290 日期1994年7月7日通过检查器（100）显示设备和检查方法。包含检查位的数据读入存储器堆栈。该装置包括通过逻辑门（30a-d）与一些存储器输入线（25）连接的第一计数器（20）和在检验器（100）和存储器（50）之间的第二计数器），其通过第一（20）和第二（80）通过逻辑门（70a-d）连接到与存储器输入线（25）对应的存储器输出线（55）。计数器产生连续的二进制值。该方法包括以下阶段：根据异或运算将待读取的数据与由第一计数器（20）生成的值的组合; 将逻辑组合数据读入存储器（50）; 从存储器（50）读取逻辑组合的数据; 根据异或运算，逻辑组合数据的读出与由第二计数器（80）生成的值的组合; 在奇偶校验器（100）中检查读出的奇偶校验数据。本发明可以用在两个异步定时总线之间的缓冲存储器（50）中。

5. 发明授权

US5218245A Programmable neural logic device 失效
标题翻译：可编程神经逻辑器件
公开(公告)号：US5218245A
公开(公告)日：1993-06-08
申请号：US758642
申请日：1991-09-12
申请人： Helmut Kohler , Norbert Schumacher
发明人： Helmut Kohler , Norbert Schumacher
IPC分类号： G06G7/60 , G06F15/18 , G06N3/06 , G06N3/063 , H03K19/173
CPC分类号： H03K19/1736 , G06N3/063
摘要： A programmable logic cell, compatible with LSSD (Level Sensitive Scan Design) technique, is described whose internal logic function can be initially loaded from an EPROM or external processor. The output or contents of one cell can be connected to another cell to alter the logic operation of the second cell even while this second cell is in operation. The cells can be connected together to form a neural network.
摘要翻译：描述了与LSSD（电平敏感扫描设计）技术兼容的可编程逻辑单元，其内部逻辑功能可以从EPROM或外部处理器初始加载。一个单元的输出或内容可以连接到另一单元，以改变第二单元的逻辑运算，即使该第二单元正在运行。细胞可以连接在一起形成神经网络。

6. 发明授权

US09064074B2 Retrieving odd net topology in hierarchical circuit designs 有权
标题翻译：在分层电路设计中检索奇数网络拓扑
公开(公告)号：US09064074B2
公开(公告)日：2015-06-23
申请号：US13295489
申请日：2011-11-14
申请人： Joerg Kayser , Helmut Kohler , Norbert Schumacher
发明人： Joerg Kayser , Helmut Kohler , Norbert Schumacher
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081
摘要： According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.
摘要翻译：根据本公开的一个方面，公开了一种用于在分级电子电路设计中识别奇数网络的方法和技术。该方法包括：接收电子电路设计的非常高速的集成电路硬件描述语言（VHDL）模型; 修改VHDL模型的每个端点组件的VHDL代码的架构部分，以将端点组件VHDL代码的每个输入/输出（IO）连接到窥探VHDL代码的实例; 通过多个时钟周期执行VHDL模型的模拟，同时通过窥探VHDL代码驱动逻辑值，并导出由窥探VHDL代码针对端点组件的每个IO检测到的模拟冲突; 并基于从仿真得到的模拟冲突，提取VHDL模型的奇数网络拓扑。

7. 发明授权

US07379470B2 Combined and data compressed FIFO based arbitration for a non-blocking switch 失效
标题翻译：用于非阻塞开关的组合和数据压缩基于FIFO的仲裁
公开(公告)号：US07379470B2
公开(公告)日：2008-05-27
申请号：US10425133
申请日：2003-04-28
申请人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
发明人： Francois Abel , Gottfried Andreas Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
IPC分类号： H04L12/54
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译：一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

8. 发明申请

US20130124182A1 RETRIEVING ODD NET TOPOLOGY IN HIERARCHICAL CIRCUIT DESIGNS 有权
标题翻译：在分层电路设计中检索ODD网络拓扑
公开(公告)号：US20130124182A1
公开(公告)日：2013-05-16
申请号：US13295489
申请日：2011-11-14
申请人： Joerg Kayser , Helmut Kohler , Norbert Schumacher
发明人： Joerg Kayser , Helmut Kohler , Norbert Schumacher
IPC分类号： G06F17/50
CPC分类号： G06F17/5045 , G06F17/5081
摘要： According to one aspect of the present disclosure, a method and technique for identifying odd nets in a hierarchical electronic circuit design is disclosed. The method includes: receiving a very high-speed integrated circuit hardware description language (VHDL) model of an electronic circuit design; modifying an architecture section of VHDL code of each endpoint component of the VHDL model to connect each input/output (IO) of the endpoint component VHDL code to an instance of a snoop VHDL code; executing a simulation of the VHDL model through a plurality of clock cycles while driving a logical value by the snoop VHDL code and deriving simulation clashes detected by the snoop VHDL code for each IO of the endpoint components; and extracting an odd net topology for the VHDL model based on the simulation clashes derived from the simulation.
摘要翻译：根据本公开的一个方面，公开了一种用于在分级电子电路设计中识别奇数网络的方法和技术。该方法包括：接收电子电路设计的非常高速的集成电路硬件描述语言（VHDL）模型; 修改VHDL模型的每个端点组件的VHDL代码的架构部分，以将端点组件VHDL代码的每个输入/输出（IO）连接到窥探VHDL代码的实例; 通过多个时钟周期执行VHDL模型的模拟，同时通过窥探VHDL代码驱动逻辑值，并导出由窥探VHDL代码针对端点组件的每个IO检测到的模拟冲突; 并基于从仿真得到的模拟冲突，提取VHDL模型的奇数网络拓扑。

9. 发明申请

US20050099945A1 Combined and data compressed fifo based arbitration for a non-blocking switch 失效
标题翻译：用于非阻塞开关的组合和数据压缩基于fifo的仲裁
公开(公告)号：US20050099945A1
公开(公告)日：2005-05-12
申请号：US10425133
申请日：2003-04-28
申请人： Francois Abel , Gottfried Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
发明人： Francois Abel , Gottfried Goldrian , Ingemar Holm , Helmut Kohler , Norbert Schumacher
IPC分类号： H04J3/14 , H04L12/56
CPC分类号： H04L49/90 , H04L2012/5679
摘要： A method and system for switching data packets through a multiple (m) input, multiple (n) output switching device providing a switching method having a fast one-cycle throughput. A respective switching device behaves like an output queued switch from a set of distributed output queues reading the incoming input control information from the plurality of input ports (IP) and compresses the information in a form which allows an easy association with a respective output port (OP) to which an individual input port is temporarily mapped.
摘要翻译：一种用于通过多输入（n）输出切换装置切换数据分组的方法和系统，其提供具有快速一周期吞吐量的切换方法。相应的交换设备的行为类似于从多个输入端口（IP）读取输入输入控制信息的一组分布式输出队列的输出排队交换机，并以允许与相应输出端口（...）容易关联的形式来压缩信息 OP），单个输入端口临时映射到该端口。

10. 发明授权

US4615424A Friction clutch 失效
标题翻译：摩擦离合器
公开(公告)号：US4615424A
公开(公告)日：1986-10-07
申请号：US509190
申请日：1983-06-29
申请人： Helmut Kohler
发明人： Helmut Kohler
IPC分类号： F16D13/70 , F16D13/71 , F16D13/58
CPC分类号： F16D13/71 , F16D2013/706 , Y10T29/4994 , Y10T29/4995 , Y10T29/49954
摘要： The axially movable pressure plate of a friction clutch for motor vehicles is non-rotatably secured to the housing by a set of leaf springs each of which has an end portion overlying that surface of the pressure plate which faces away from the clutch plate. The end portion of each leaf spring has an opening in register with the open end of a blind bore in the surface of the pressure plate. Such end portions of the leaf springs are permanently fastened to the pressure plate by tubular connecting elements having (a) enlarged end portions overlying those sides of the leaf springs which face away from the pressure plate and (b) main portions which extend through the respective openings and into the registering blind bores and are radially expanded into pronounced frictional engagement with the pressure plate. The plastically deformable material of the main portions of the connecting elements is expanded by an extractible tool or by discrete spreading pins which are driven into open-ended sockets of the connecting elements and remain therein to maintain the main portions in radially expanded condition. The connecting elements contribute to a reduction of the overall weight of the friction clutch, to a reduction of the dimensions of the clutch, as considered in the axial and radial directions, to a reduction of the weight of the clutch, and to greater reliability of the connections between the leaf springs and the pressure plate and hence to greater safety of the clutch.
摘要翻译：用于机动车辆的摩擦离合器的可轴向移动的压板通过一组板簧不可旋转地固定到壳体，每个板簧的顶部覆盖压板的远离离合器板的表面。每个板簧的端部具有与压板表面中的盲孔的开口端对齐的开口。板簧的这种端部通过管状连接元件永久地固定到压板上，该连接元件具有（a）覆盖板簧的面向远离压板的那些侧面的扩大的端部，以及（b）延伸穿过相应的主要部分的主要部分开口并进入登记盲孔并且径向扩张成与压板明显的摩擦接合。连接元件的主要部分的可塑性变形的材料通过可抽出的工具或分散的扩展销扩张，这些销被驱动到连接元件的开口插座中并保持在其中，以使主要部分保持在径向膨胀的状态。连接元件有助于减小摩擦离合器的总重量，从而在轴向和径向方向上考虑到离合器的尺寸减小到离合器的重量的降低，并且具有更高的可靠性板簧与压板之间的连接，从而提高了离合器的安全性。

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