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1. 发明授权

US5502954A Flap folding device of wrapping machine 失效
标题翻译：包装机折边装置
公开(公告)号：US5502954A
公开(公告)日：1996-04-02
申请号：US181238
申请日：1994-01-13
申请人： Heiemon Akiyama , Masafumi Hamaguchi , Minoru Sato , Hiroaki Kikuta
发明人： Heiemon Akiyama , Masafumi Hamaguchi , Minoru Sato , Hiroaki Kikuta
IPC分类号： B65B11/22 , B65B49/08
CPC分类号： B65B49/08 , B65B11/22 , B65B25/14 , B65B51/06
摘要： Flap folding device of a wrapping machine. Side folding guides approach side flaps to hit a hitting part against the closed side faces of a wrapped body part of a content or volume, thereby pressing a wrapped body part, near the base end of the side flaps that face the closed side faces, against the closed side faces. Subsequently, the middle part of each of the side folding guides makes a quarter turn while tracing a corner continued to the closed side faces,. Therefore, the base ends of the side flaps are folded along the corners while being pulled toward the forward end thereof, and, at the same time, are pressed by folding parts against the open sides, through the entire length, from the base end to the forward end, of the side flaps.
摘要翻译：包装机的折叠折叠装置。侧折叠导板接近侧翼以抵抗内容物或体积的包裹体部分的封闭侧面撞击部分，从而将面向封闭侧面的侧翼的基端附近的包裹的身体部分压靠在封闭的侧面。随后，每个侧面折叠导轨的中间部分四分之一圈转动，同时跟踪一个角落继续到封闭的侧面。因此，侧板的基端部沿着角部被折叠，同时被拉向其前端，并且同时被折叠部分压靠在敞开的侧面，从整个长度，从基端到侧翼的前端。

2. 发明申请

US20080067633A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD FOR THE SAME 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20080067633A1
公开(公告)日：2008-03-20
申请号：US11928750
申请日：2007-10-30
申请人： Masafumi Hamaguchi
发明人： Masafumi Hamaguchi
IPC分类号： H01L29/16
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L29/1083
摘要： A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.
摘要翻译：半导体器件包括设置在半导体衬底的表面层上的锗原子和第一杂质原子的第一扩散区，具有导电性的第一杂质原子和包含第二杂质原子的第二扩散区，比第一扩散区浅扩散区域，所述第二杂质原子对所述导电性没有贡献。

3. 发明授权

US07605043B2 Semiconductor device and manufacturing method for the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07605043B2
公开(公告)日：2009-10-20
申请号：US11826117
申请日：2007-07-12
申请人： Masafumi Hamaguchi
发明人： Masafumi Hamaguchi
IPC分类号： H01L21/336
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L29/1083
摘要： A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.
摘要翻译：半导体器件包括设置在半导体衬底的表面层上的锗原子和第一杂质原子的第一扩散区，具有导电性的第一杂质原子和包含第二杂质原子的第二扩散区，比第一扩散区浅扩散区域，所述第二杂质原子对所述导电性没有贡献。

4. 发明申请

US20090173967A1 STRAINED-CHANNEL FET COMPRISING TWIST-BONDED SEMICONDUCTOR LAYER 审中-公开
标题翻译：包含TWIST-BONDED SEMICONDUCTOR LAYER的应变通道FET
公开(公告)号：US20090173967A1
公开(公告)日：2009-07-09
申请号：US11969618
申请日：2008-01-04
申请人： Masafumi Hamaguchi , Ryoji Hasumi , Haizhou Yin , Katherine L. Saenger
发明人： Masafumi Hamaguchi , Ryoji Hasumi , Haizhou Yin , Katherine L. Saenger
IPC分类号： H01L29/04 , H01L21/20 , H01L21/8238 , H01L27/092 , H01L29/778
CPC分类号： H01L21/823807 , H01L21/76251 , H01L21/823878 , H01L21/84 , H01L27/0922 , H01L27/1203 , H01L29/045 , H01L29/165 , H01L29/7843 , H01L29/7848 , H01L29/7849
摘要： This invention provides a strained-channel field effect transistor (FET) in which the semiconductor of the channel of the FET is formed in a compliant substrate layer disposed over a twist-bonded semiconductor interface. This FET geometry increases the efficacy of local stress elements such as stress liners and embedded lattice-mismatched source/drain regions by mechanically decoupling the semiconductor of the channel region from the underlying rigid substrate. These strained-channel FETs may be incorporated into complementary metal oxide semiconductor (CMOS) circuits in various combinations. In one embodiment of this invention, both pFETs and nFETs are in a twist-bonded (001) silicon layer on a (001) silicon base layer. In another embodiment, pFETs are in a twist-bonded (011) silicon layer on a (001) silicon base layer and nFETs are in a conventional, non-twist-bonded (001) silicon base layer. This invention also provides a twist-bonded semiconductor layer on a polycrystalline base layer, as well as methods for fabricating the aforementioned FETs.
摘要翻译：本发明提供了一种应变场效应晶体管（FET），其中FET的沟道的半导体形成在设置在扭曲键合的半导体界面上的柔性衬底层中。该FET几何通过机械地将沟道区域的半导体与下面的刚性衬底去耦合来增加局部应力元件（例如应力衬垫和嵌入的晶格失配的源/漏区域）的功效。这些应变通道FET可以以各种组合结合到互补金属氧化物半导体（CMOS）电路中。在本发明的一个实施例中，pFET和nFET都是（001）硅基层上的扭曲粘合（001）硅层。在另一个实施方案中，pFET在（001）硅基底层上是扭曲粘合（011）硅层，nFET是常规的非扭曲键合（001）硅基层。本发明还提供了在多晶基底层上的扭曲键合半导体层以及制造上述FET的方法。

5. 发明授权

US07271443B2 Semiconductor device and manufacturing method for the same 失效
标题翻译：半导体器件及其制造方法相同
公开(公告)号：US07271443B2
公开(公告)日：2007-09-18
申请号：US11079520
申请日：2005-03-15
申请人： Masafumi Hamaguchi
发明人： Masafumi Hamaguchi
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L29/1083
摘要： A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.
摘要翻译：半导体器件包括设置在半导体衬底的表面层上的锗原子和第一杂质原子的第一扩散区，具有导电性的第一杂质原子和包含第二杂质原子的第二扩散区，比第一扩散区浅扩散区域，所述第二杂质原子对所述导电性没有贡献。

6. 发明申请

US20110230030A1 STRAIN-PRESERVING ION IMPLANTATION METHODS 失效
标题翻译：应变保留离子植入方法
公开(公告)号：US20110230030A1
公开(公告)日：2011-09-22
申请号：US12724608
申请日：2010-03-16
申请人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
发明人： Joel P. de Souza , Masafumi Hamaguchi , Ahmet S. Ozcan , Devendra K. Sadana , Katherine L. Saenger , Donald R. Wall
IPC分类号： H01L21/336
CPC分类号： H01L21/26506 , H01L21/324 , H01L29/165 , H01L29/6659 , H01L29/7833 , H01L29/7848
摘要： An embedded epitaxial semiconductor portion having a different composition than matrix of the semiconductor substrate is formed with a lattice mismatch and epitaxial alignment with the matrix of the semiconductor substrate. The temperature of subsequent ion implantation steps is manipulated depending on the amorphizing or non-amorphizing nature of the ion implantation process. For a non-amorphizing ion implantation process, the ion implantation processing step is performed at an elevated temperature, i.e., a temperature greater than nominal room temperature range. For an amorphizing ion implantation process, the ion implantation processing step is performed at nominal room temperature range or a temperature lower than nominal room temperature range. By manipulating the temperature of ion implantation, the loss of strain in a strained semiconductor alloy material is minimized.
摘要翻译：具有与半导体衬底的矩阵不同的组成的嵌入式外延半导体部分与半导体衬底的矩阵形成晶格失配和外延对准。随后离子注入步骤的温度根据离子注入工艺的非晶化或非非晶化性质进行操作。对于非非晶化离子注入工艺，离子注入处理步骤在升高的温度，即大于标称室温范围的温度下进行。对于非晶化离子注入工艺，离子注入处理步骤在标称室温范围或低于标称室温范围的温度下进行。通过操纵离子注入的温度，使应变半导体合金材料中的应变损失最小化。

7. 发明申请

US20100327395A1 SEMICONDUCTOR DEVICE ON DIRECT SILICON BONDED SUBSTRATE WITH DIFFERENT LAYER THICKNESS 失效
标题翻译：具有不同层厚度的直接硅粘结基板上的半导体器件
公开(公告)号：US20100327395A1
公开(公告)日：2010-12-30
申请号：US12493469
申请日：2009-06-29
申请人： Masafumi Hamaguchi , Ryoji Hasumi
发明人： Masafumi Hamaguchi , Ryoji Hasumi
IPC分类号： H01L29/06 , H01L21/76 , H01L21/18
CPC分类号： H01L29/045 , H01L21/02381 , H01L21/02433 , H01L21/02532 , H01L21/02609 , H01L21/02639 , H01L21/02667 , H01L21/187 , H01L21/26506 , H01L21/823412 , H01L21/823807 , H01L29/1054
摘要： A Direct Silicon Bonded substrate can include a first substrate and a second substrate in which the second substrate can be rotated to an azimuthal twist angle of 45 degrees in comparison to the first substrate. Disclosed are a semiconductor device and a method for making a semiconductor device that includes a DSB substrate with an adjusted thickness based upon the threshold voltage (Vt). In other words, a thicker substrate or layer can correspond to a high threshold voltage (HVt) and a thinner substrate or layer can correspond to a low threshold voltage (LVt) in order to improve mobility in LVt devices.
摘要翻译：直接硅键合衬底可以包括第一衬底和第二衬底，其中与第一衬底相比，第二衬底可以旋转到45度的方位角扭转角。公开了一种用于制造半导体器件的半导体器件和方法，该半导体器件包括基于阈值电压（Vt）的具有调整厚度的DSB衬底。换句话说，较厚的衬底或层可以对应于高阈值电压（HVt），并且较薄的衬底或层可以对应于低阈值电压（LVt），以便提高LVt器件中的移动性。

8. 发明申请

US20060046415A1 Semiconductor device and manufacturing method for the same 失效
公开(公告)号：US20060046415A1
公开(公告)日：2006-03-02
申请号：US11079520
申请日：2005-03-15
申请人： Masafumi Hamaguchi
发明人： Masafumi Hamaguchi
IPC分类号： H01L21/331
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L29/1083
摘要： A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.

9. 发明申请

US20120080777A1 TRIPLE OXIDATION ON DSB SUBSTRATE 审中-公开
标题翻译： DSB基板上的三重氧化
公开(公告)号：US20120080777A1
公开(公告)日：2012-04-05
申请号：US12895095
申请日：2010-09-30
申请人： Masafumi Hamaguchi , Ryoji Hasumi
发明人： Masafumi Hamaguchi , Ryoji Hasumi
IPC分类号： H01L29/78 , H01L21/314
CPC分类号： H01L21/02238 , H01L21/823412 , H01L21/823462 , H01L21/823481 , H01L21/823807 , H01L21/823857 , H01L21/823878
摘要： According to certain embodiments, a semiconductor structure is formed having a gate oxide formed over a semiconductor substrate. The gate oxide is formed as to have three different regions characterized by a different average thickness of gate oxide in each region. A first oxidation process is performed on a semiconductor substrate having both a Si (110) orientation region and a Si (100) orientation region on a surface thereof. Gate oxide is formed at a faster rate on the Si (110) orientation region of the semiconductor substrate relative to the Si (100) orientation region. A portion of the gate oxide is selectively removed and a second oxidation process is performed to form additional gate oxide. A triple oxide semiconductor substrate is recovered with the gate oxide having three different thickness formed thereon. The triple oxide semiconductor substrate is formed using a decreased number of processing acts.
摘要翻译：根据某些实施例，形成在半导体衬底上形成栅极氧化物的半导体结构。栅极氧化物形成为具有三个不同的区域，其特征在于每个区域中栅极氧化物的平均厚度不同。在其表面上具有Si（110）取向区域和Si（100）取向区域的半导体衬底上进行第一氧化工艺。栅极氧化物以相对于Si（100）取向区域在半导体衬底的Si（110）取向区域上以更快的速率形成。选择性地去除栅极氧化物的一部分，并且执行第二氧化工艺以形成另外的栅极氧化物。用形成有三个不同厚度的栅极氧化物回收三重氧化物半导体衬底。使用减少数量的处理作用形成三重氧化物半导体衬底。

10. 发明授权

US07514763B2 Semiconductor device and manufacturing method for the same 失效
公开(公告)号：US07514763B2
公开(公告)日：2009-04-07
申请号：US11928750
申请日：2007-10-30
申请人： Masafumi Hamaguchi
发明人： Masafumi Hamaguchi
IPC分类号： H01L29/167 , H01L29/207 , H01L29/227 , H01L31/0288
CPC分类号： H01L29/6659 , H01L21/26506 , H01L21/2652 , H01L21/26586 , H01L29/1083
摘要： A semiconductor device includes a first diffusion region including germanium atoms and first impurity atoms, provided on a surface layer of a semiconductor substrate, the first impurity atoms contributing to electric conductivity, and a second diffusion region including second impurity atoms, provided shallower than the first diffusion region from a surface of the first diffusion region, the second impurity atoms not contributing to the electric conductivity.

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