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1. 发明申请

US20100283154A1 SPUTTERING TARGET AND SEMICONDUCTOR DEVICE MANUFACTURED USING THE SAME 失效
标题翻译：使用其制造的溅射目标和半导体器件
公开(公告)号：US20100283154A1
公开(公告)日：2010-11-11
申请号：US12573437
申请日：2009-10-05
申请人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-Kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
发明人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-Kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L23/532 , C23C14/14
CPC分类号： H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %.
摘要翻译：溅射靶包括钨（W） - 镍（Ni）合金，其中镍（Ni）以约0.01重量％至约1重量％的量存在。

2. 发明授权

US07718520B2 Semiconductor integrated circuit device and related method 有权
标题翻译：半导体集成电路器件及相关方法
公开(公告)号：US07718520B2
公开(公告)日：2010-05-18
申请号：US11723725
申请日：2007-03-21
申请人： Hee-sook Park
发明人： Hee-sook Park
IPC分类号： H01L21/00
CPC分类号： H01L27/105 , H01L27/1052 , H01L29/66628
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第1层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

3. 发明授权

US07518214B2 Semiconductor device and method of fabricating the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07518214B2
公开(公告)日：2009-04-14
申请号：US11586610
申请日：2006-10-26
申请人： Dong-chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
发明人： Dong-chan Lim , Byung-hee Kim , Tae-ho Cha , Hee-sook Park , Geum-jung Seong
IPC分类号： H01L29/00
CPC分类号： H01L21/28061 , H01L21/28114 , H01L29/42376 , H01L29/4941 , H01L29/517 , H01L29/518 , H01L29/6656
摘要： An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers. The etching is preferably a process of etching the barrier layer in situ using an etchant having an etch selectivity between the material of the barrier layer and the materials constituting the other layers of the line.
摘要翻译：半导体器件的集成电路具有不易发生严重RC延迟的线型图案。该集成电路具有由至少一层多晶硅，具有低薄层电阻的金属层和介于多晶硅和具有低薄层电阻的金属之间的阻挡金属层形成的线，以及第一间隔物分别布置在线的侧面上，其特征在于，线在阻挡层的侧面具有凹槽，并且第一间隔件填充凹部。集成电路可以构成半导体器件的栅极线。集成电路通过以下方式形成：将多层硅，具有低薄层电阻的金属和阻挡金属层叠在一起形成，将层图案化成一条线，蚀刻其形成凹部，然后形成第一间隔物。蚀刻优选是使用在阻挡层的材料和构成线的其它层的材料之间具有蚀刻选择性的蚀刻剂原位蚀刻阻挡层的工艺。

4. 发明授权

US07223689B2 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 有权
标题翻译：在形成阻挡金属层的同时形成欧姆层的半导体器件中形成金属接触的方法
公开(公告)号：US07223689B2
公开(公告)日：2007-05-29
申请号：US11112356
申请日：2005-04-22
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.
摘要翻译：通过在硅衬底上形成具有接触孔的绝缘层，形成半导体器件中的金属接触。钴层形成在接触孔的底壁和内壁上。在钴层上形成钛层的同时，在接触孔的底部形成钴硅化物层。在钛层上形成插塞以填充接触孔。

5. 发明授权

US06277764B1 Interlayered dielectric layer of semiconductor device and method of manufacturing the same 有权
标题翻译：半导体器件的层间绝缘层及其制造方法
公开(公告)号：US06277764B1
公开(公告)日：2001-08-21
申请号：US09224560
申请日：1998-12-30
申请人： Hong-jae Shin , Hee-sook Park , Sung-jin Kim
发明人： Hong-jae Shin , Hee-sook Park , Sung-jin Kim
IPC分类号： H01L2131
CPC分类号： H01L21/02131 , H01L21/02134 , H01L21/022 , H01L21/02211 , H01L21/02274 , H01L21/02282 , H01L21/31053 , H01L21/3124 , H01L21/3127 , H01L21/314 , H01L21/31629 , H01L21/76801 , H01L21/76835 , H01L21/76837
摘要： A method of forming an interlayer dielectric layer of a semiconductor device and an interlayer dielectric layer using the same. By the method, a semiconductor substrate formed metal interconnect lines thereon is provided, a first insulating layer of a low dielectric material is formed on the semiconductor substrate, by a spin coating, and a second insulating layer of a low dielectric material is formed on the first insulating layer, by the high density plasma chemical vapor deposition (CVD). The second insulating layer is planarized through a chemical mechanical polishing (CMP) process.
摘要翻译：一种形成半导体器件的层间电介质层的方法和使用其的层间电介质层。通过该方法，在其上形成有金属互连线的半导体衬底，通过旋涂在半导体衬底上形成低介电材料的第一绝缘层，并且在第二绝缘层上形成低电介质材料的第二绝缘层第一绝缘层，通过高密度等离子体化学气相沉积（CVD）。通过化学机械抛光（CMP）工艺对第二绝缘层进行平面化处理。

6. 发明申请

US20080070405A1 Methods of forming metal wiring layers for semiconductor devices 审中-公开
标题翻译：形成半导体器件的金属布线层的方法
公开(公告)号：US20080070405A1
公开(公告)日：2008-03-20
申请号：US11800996
申请日：2007-05-08
申请人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
发明人： Jae-hwa Park , Gil-heyun Choi , Jong-myeong Lee , Hee-sook Park
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/76856
摘要： A method of forming a conductive plug for an integrated circuit device may include forming an insulating layer on an integrated circuit substrate with the insulating layer having a surface opposite the substrate and a recess therein. A titanium (Ti) layer may be formed on sidewalls of the recess and on the surface of the insulating layer opposite the substrate. After forming the titanium (Ti) layer, a reaction reducing layer may be formed on portions of the titanium layer on the surface of the insulating layer opposite the substrate by at least one of ionized physical vapour deposition (iPVD) and/or nitriding a portion of the titanium layer, and the reaction reducing layer may include a material other than titanium. After forming the reaction reducing layer, a TiN layer may be formed on the reaction reducing layer and on sidewalls of the recess in the insulating layer using metal organic chemical vapour deposition (MOCVD). After forming the TiN layer, a conductive plug may be formed on the TiN layer in the recess in the insulating layer.
摘要翻译：形成用于集成电路器件的导电插塞的方法可以包括在集成电路衬底上形成绝缘层，绝缘层具有与衬底相对的表面和凹槽。钛（Ti）层可以形成在凹槽的侧壁上，并且在绝缘层的与衬底相对的表面上。在形成钛（Ti）层之后，可以通过离子物理气相沉积（iPVD）和/或氮化一部分中的至少一种，在绝缘层的与基板相对的表面上的钛层的部分上形成反应还原层的钛层，反应还原层可以包括钛以外的材料。在形成反应还原层之后，可以使用金属有机化学气相沉积（MOCVD）在反应还原层上和在绝缘层的凹槽的侧壁上形成TiN层。在形成TiN层之后，可以在绝缘层的凹部中的TiN层上形成导电塞。

7. 发明申请

US20070221998A1 Semiconductor integrated circuit device and related method 有权
标题翻译：半导体集成电路器件及相关方法
公开(公告)号：US20070221998A1
公开(公告)日：2007-09-27
申请号：US11723725
申请日：2007-03-21
申请人： Hee-sook Park
发明人： Hee-sook Park
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L27/105 , H01L27/1052 , H01L29/66628
摘要： Embodiments of the invention provide a semiconductor integrated circuit device and a method for fabricating the device. In one embodiment, the method comprises forming a plurality of preliminary gate electrode structures in a cell array region and a peripheral circuit region of a semiconductor substrate; forming selective epitaxial films on the semiconductor substrate in the cell array region and the peripheral region; implanting impurities into at least some of the selective epitaxial films to form elevated source/drain regions in the cell array region and the peripheral circuit region; forming a first interlayer insulating film; and patterning the first interlayer insulating film to form a plurality of first openings exposing the elevated source/drain regions. The method further comprises forming a first ohmic film, a first barrier film, and a metal film; and removing portions of each of the metal film, the first barrier film, and the first ohmic film.
摘要翻译：本发明的实施例提供一种半导体集成电路器件及其制造方法。在一个实施例中，该方法包括在半导体衬底的单元阵列区域和外围电路区域中形成多个预选栅电极结构; 在电池阵列区域和外围区域中的半导体衬底上形成选择性外延膜; 将杂质注入到至少一些选择性外延膜中以在电池阵列区域和外围电路区域中形成升高的源极/漏极区域; 形成第一层间绝缘膜; 以及图案化所述第一层间绝缘膜以形成暴露所述升高的源极/漏极区域的多个第一开口。该方法还包括形成第一欧姆膜，第一阻挡膜和金属膜; 以及去除金属膜，第一阻挡膜和第一欧姆膜中的每一个的部分。

8. 发明申请

US20070197015A1 Methods for forming a metal contact in a semiconductor device in which an ohmic layer is formed while forming a barrier metal layer 审中-公开
公开(公告)号：US20070197015A1
公开(公告)日：2007-08-23
申请号：US11787468
申请日：2007-04-17
申请人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
发明人： Hee-sook Park , Gil-heyun Choi , Sang-bum Kang , Seong-geon Park , Kwang-jin Moon
IPC分类号： H01L21/44
CPC分类号： H01L21/76843 , H01L21/28518 , H01L21/2855 , H01L21/28556 , H01L21/76846 , H01L21/76855 , H01L21/76858
摘要： A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.

9. 发明授权

US06485815B1 Multi-layered dielectric layer including insulating layer having Si-CH3 bond therein and method for fabricating the same 有权
标题翻译：包含其中具有Si-CH3键的绝缘层的多层电介质层及其制造方法
公开(公告)号：US06485815B1
公开(公告)日：2002-11-26
申请号：US09577075
申请日：2000-05-23
申请人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
发明人： Hyun-dam Jeong , Hee-sook Park , Hong-jae Shin , Byeong-jun Kim
IPC分类号： B32B2700
CPC分类号： H01L23/53295 , C04B35/5603 , C04B35/565 , H01L21/02137 , H01L21/0214 , H01L21/02282 , H01L21/02332 , H01L21/0234 , H01L21/02362 , H01L21/3122 , H01L21/76801 , H01L21/76826 , H01L21/76829 , H01L21/76835 , H01L23/5222 , H01L23/5226 , H01L23/5329 , H01L2924/0002 , Y10T428/24843 , Y10T428/24926 , Y10T428/263 , Y10T428/31663 , H01L2924/00
摘要： A multi-layered dielectric layer wherein the adhesion characteristic of an insulating layer including a Si—CH3 bond is improved, and a method of forming the same are provided. The multi-layered dielectric layer is formed on conductive patterns and includes a first insulating layer formed of a layer having a low dielectric constant including the Si—CH3 bond. In order to improve the adhesion characteristic of the first insulating layer, an adhesion surface is formed on the surface of the first insulating layer by treating the first insulating layer with plasma. In an alternative, the adhesion characteristics of the first insulating layer is improved by forming a buffer layer on the first insulating layer so that dipole-dipole interaction occurs between the first insulating layer and the buffer layer.
摘要翻译：提供了包括Si-CH 3键的绝缘层的粘合特性的多层电介质层，并且提供了其形成方法。多层电介质层形成在导电图案上，并且包括由具有包含Si-CH3键的低介电常数的层形成的第一绝缘层。为了改善第一绝缘层的附着特性，通过用等离子体处理第一绝缘层，在第一绝缘层的表面上形成粘合表面。或者，通过在第一绝缘层上形成缓冲层，在第一绝缘层和缓冲层之间产生偶极 - 偶极相互作用，来提高第一绝缘层的粘合特性。

10. 发明授权

US07956464B2 Sputtering target and semiconductor device manufactured using the same 失效
标题翻译：溅射靶和使用其制造的半导体器件
公开(公告)号：US07956464B2
公开(公告)日：2011-06-07
申请号：US12573437
申请日：2009-10-05
申请人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
发明人： Taek-jung Kim , Hee-sook Park , Jong-min Back , Su-kyoung Kim , Yu-gyun Shin , Sun-ghil Lee
IPC分类号： H01L23/532
CPC分类号： H01L23/53266 , C23C14/185 , C23C14/3414 , H01L21/28088 , H01L2924/0002 , H01L2924/00
摘要： A sputtering target includes a tungsten (W)-nickel (Ni) alloy, wherein the nickel (Ni) is present in an amount of between about 0.01 weight % and about 1 weight %.
摘要翻译：溅射靶包括钨（W） - 镍（Ni）合金，其中镍（Ni）的存在量为约0.01重量％至约1重量％。

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