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1. 发明申请

US20140014827A1 INFRARED SENSOR CHIP, INFRARED DETECTOR AND METHOD FOR OEPRATING AND TESTING THE SAME 审中-公开
标题翻译：红外传感器芯片，红外探测器及其测试和测试方法
公开(公告)号：US20140014827A1
公开(公告)日：2014-01-16
申请号：US13997262
申请日：2012-03-05
申请人： Hee Yeoun Kim , Jae Hong Park , Kwy Ro Lee , Gyung Tae Kim , Kyoung Min Kim , Byeong IL Kim , Ki Myeong Kyung
发明人： Hee Yeoun Kim , Jae Hong Park , Kwy Ro Lee , Gyung Tae Kim , Kyoung Min Kim , Byeong IL Kim , Ki Myeong Kyung
IPC分类号： G01J5/24
CPC分类号： G01J5/24 , G01J5/026 , G01J5/20 , H01L2224/48091 , H01L2224/48137 , H01L2224/49175 , H01L2924/1305 , H01L2924/13055 , H01L2924/1461 , H01L2924/3011 , H01L2924/00014 , H01L2924/00
摘要： According to the embodiment of the present invention, an infrared sensor chip may be provided that includes: a CMOS circuit board comprised of an active matrix, a row line selector and an output multiplexer; and a bolometer which is stacked on the CMOS circuit board and is comprised of an active cell and a reference cell, wherein, for the purpose of a parametric test for the bolometer at a wafer or chip state, the row line selector selects a cell to which a voltage is applied in the bolometer, and wherein the output multiplexer outputs current characteristics according to the voltage application.
摘要翻译：根据本发明的实施例，可以提供一种红外线传感器芯片，其包括：由有源矩阵，行线选择器和输出多路复用器组成的CMOS电路板; 和位于CMOS电路板上并由活性电池和参考电池组成的测辐射热计，其中，为了在晶圆或芯片状态下用于测辐射热计的参数测试，行线选择器选择一个单元其中在测辐射热计中施加电压，并且其中输出多路复用器根据电压施加输出电流特性。

2. 发明授权

US07830205B2 Fuse circuit for use in a semiconductor integrated apparatus 有权
标题翻译：用于半导体集成设备的保险丝电路
公开(公告)号：US07830205B2
公开(公告)日：2010-11-09
申请号：US12171233
申请日：2008-07-10
申请人： Gyung Tae Kim
发明人： Gyung Tae Kim
IPC分类号： G11C17/16 , G06F11/20
CPC分类号： G11C17/16 , G11C29/787 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit of a semiconductor integrated apparatus includes first and second fuse blocks. The first fuse block includes a first up fuse block where a first plurality of fuses are arranged and a first down fuse block where a second plurality of fuses are arranged. The second plurality of fuses comprises fewer fuses than the first plurality of fuses. The second fuse block includes a second up fuse block where a third plurality of fuses are arranged, the third plurality of fuses comprising the same number of fuses as the second plurality of fuses, and a second down fuse block that includes a fourth plurality of fuses, the fourth plurality of fuses comprising the same number of fuses as the first plurality of fuses. The first up fuse block is opposite the second up fuse block and the first down fuse block is opposite the second down fuse block.
摘要翻译：半导体集成装置的熔丝电路包括第一和第二熔丝块。第一熔丝块包括布置有第一多个熔丝的第一上熔丝块和布置有第二多个保险丝的第一下熔丝块。第二组保险丝包括比第一组多个保险丝更少的保险丝。第二保险丝盒包括第二上保险丝盒，其中布置有第三多个保险丝，第三多个保险丝包括与第二多个保险丝相同数量的保险丝，以及包括第四多个保险丝的第二保险丝盒，第四组保险丝包括与第一组多个保险丝相同数量的保险丝。第一个保险丝盒与第二个保险丝盒相对，第一个下降的保险丝盒与第二个保险丝盒相对。

3. 发明授权

US08891325B2 Circuit for driving word line 有权
标题翻译：电路驱动字线
公开(公告)号：US08891325B2
公开(公告)日：2014-11-18
申请号：US13602254
申请日：2012-09-03
申请人： Byeong Chan Choi , Gyung Tae Kim
发明人： Byeong Chan Choi , Gyung Tae Kim
IPC分类号： G11C8/08
CPC分类号： G11C8/14 , G11C8/08 , G11C29/02 , G11C29/024 , G11C2029/1202
摘要： A word line driving circuit includes, inter alia: a word line driving signal generator, a main word line enable signal controller, and a sub word line driver. The word line driving signal generator activates a word line boosting signal, a pre-main word line enable signal, and a word line off signal in response to an active signal and a precharge signal. The main word line enable signal controller receives the pre-main word line enable signal and outputs it as the main word line enable signal in response to a main word line test mode signal. The sub word line driver uses the word line boosting signal as a driving voltage, and drives a sub word line in response to the main word line enable signal and the word line off signal.
摘要翻译：字线驱动电路尤其包括字线驱动信号发生器，主字线使能信号控制器和子字线驱动器。字线驱动信号发生器响应于有源信号和预充电信号而激活字线升压信号，预主字线使能信号和字线截止信号。主字符串使能信号控制器接收主字幕的使能信号，并根据主字线测试模式信号将其作为主字线使能信号输出。子字线驱动器使用字线升压信号作为驱动电压，并且响应于主字线使能信号和字线关断信号驱动子字线。

4. 发明申请

US20110075498A1 SEMICONDUCTOR MEMORY APPARATUS AND TEST METHOD USING THE SAME 有权
标题翻译：半导体存储器和使用它的测试方法
公开(公告)号：US20110075498A1
公开(公告)日：2011-03-31
申请号：US12650491
申请日：2009-12-30
申请人： Choung Ki Song , Young Do Hur , Sang Sic Yoon , Yong Gu Kang , Gyung Tae Kim
发明人： Choung Ki Song , Young Do Hur , Sang Sic Yoon , Yong Gu Kang , Gyung Tae Kim
IPC分类号： G11C29/00 , G11C7/00
CPC分类号： G11C29/12 , G11C11/401 , G11C2029/1204
摘要： A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.
摘要翻译：半导体存储装置包括：预充电电压控制单元，被配置为响应于测试信号选择性地输出位线预充电电压或核心电压作为控制电压; 位线均衡单元，被配置为将位线预充电到所述控制电压; 感测放大器驱动控制单元，被配置为响应于测试信号产生第一电压供应控制信号，第二电压供应控制信号和第三电压供应控制信号，感测放大器使能测试信号，第一电压供应信号，第二电压供给信号和第三电压供给信号; 以及电压供给单元，被配置为响应于所述第一至第三电压供给控制信号，将具有开放位线结构的所述核心电压，外部电压和接地电压提供给具有开放位线结构的读出放大器。

5. 发明授权

US08687447B2 Semiconductor memory apparatus and test method using the same 有权
标题翻译：半导体存储器及使用其的测试方法
公开(公告)号：US08687447B2
公开(公告)日：2014-04-01
申请号：US12650491
申请日：2009-12-30
申请人： Choung Ki Song , Young Do Hur , Sang Sic Yoon , Yong Gu Kang , Gyung Tae Kim
发明人： Choung Ki Song , Young Do Hur , Sang Sic Yoon , Yong Gu Kang , Gyung Tae Kim
IPC分类号： G11C7/00 , G11C29/00
CPC分类号： G11C29/12 , G11C11/401 , G11C2029/1204
摘要： A semiconductor memory apparatus includes: a precharge voltage control unit configured to selectively output a bit line precharge voltage or a core voltage as a control voltage in response to a test signal; a bit line equalization unit configured to precharge a bit line to the control voltage; a sense amplifier driving control unit configured to generate a first voltage supply control signal, a second voltage supply control signal and a third voltage supply control signal in response to the test signal, a sense amplifier enable test signal, a first voltage supply signal, a second voltage supply signal and a third voltage supply signal; and a voltage supply unit configured to provide the core voltage, an external voltage and a ground voltage to a sense amplifier with an open bit line structure in response to the first to third voltage supply control signals.
摘要翻译：半导体存储装置包括：预充电电压控制单元，被配置为响应于测试信号选择性地输出位线预充电电压或核心电压作为控制电压; 位线均衡单元，被配置为将位线预充电到所述控制电压; 感测放大器驱动控制单元，被配置为响应于测试信号产生第一电压供应控制信号，第二电压供应控制信号和第三电压供应控制信号，感测放大器使能测试信号，第一电压供应信号，第二电压供给信号和第三电压供给信号; 以及电压供给单元，被配置为响应于所述第一至第三电压供给控制信号，将具有开放位线结构的所述核心电压，外部电压和接地电压提供给具有开放位线结构的读出放大器。

6. 发明申请

US20090179690A1 FUSE CIRCUIT FOR USE IN A SEMICONDUCTOR INTEGRATED APPARATUS 有权
标题翻译：用于半导体集成装置的保险丝电路
公开(公告)号：US20090179690A1
公开(公告)日：2009-07-16
申请号：US12171233
申请日：2008-07-10
申请人： Gyung Tae Kim
发明人： Gyung Tae Kim
IPC分类号： H01H37/76
CPC分类号： G11C17/16 , G11C29/787 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit of a semiconductor integrated apparatus includes a first fuse block and a second fuse block. The first fuse block includes a first up fuse block that includes a plurality of fuses, and a first down fuse block that includes fuses less than the number of fuses of the first up fuse block. The second up fuse block includes a second up fuse block that includes the same number of fuses as the first down fuse block, and a second down fuse block that includes the same number of fuses as the first up fuse block. Structures of the first up fuse block and the first down fuse block are asymmetric, and the structures of the second up fuse block and the second down fuse block are asymmetric.
摘要翻译：半导体集成装置的熔丝电路包括第一熔丝块和第二熔丝块。第一熔丝块包括包括多个熔丝的第一上熔丝块和包括小于第一上熔丝块的熔丝数的熔丝的第一下熔丝块。第二个上升的熔断器块包括一个第二个上升的熔丝块，它包含与第一个下降的熔断器块相同数量的保险丝，以及一个第二个向下的熔断器块，它包含与第一个上拉熔断器块相同数量的保险丝。第一个上升保险丝块和第一个下降保险丝块的结构是不对称的，并且第二个上升保险丝块和第二个下拉保险丝块的结构是不对称的。

7. 发明授权

US08395964B2 Row address decoder and semiconductor memory device having the same 失效
标题翻译：行地址解码器和具有其的半导体存储器件
公开(公告)号：US08395964B2
公开(公告)日：2013-03-12
申请号：US13309818
申请日：2011-12-02
申请人： Gyung Tae Kim
发明人： Gyung Tae Kim
IPC分类号： G11C8/00
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/14 , G11C8/20 , G11C29/18 , G11C2029/1202 , G11C2029/1802 , G11C2029/2602
摘要： A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight to main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.
摘要翻译：行地址解码器包括第一主字线解码单元，用于对第一和第二行地址进行解码，以产生第一至第四主解码信号。当执行数据存储测试时，第一至第四主解码信号分别在第一至第四定时被使能。行地址解码器还包括第二主字线解码单元，用于解码第三和第四行地址以产生第五至第八主解码信号。当执行数据存储测试时，分别在第一至第四定时使能第五至八对主解码信号。主字符串使能信号产生单元对第一至第四主要解码信号和第五至第八主要解码信号进行解码，以产生在不同时间使能的第一至第十六主要字线使能信号。

8. 发明授权

US08072835B2 Row address decoder and semiconductor memory device having the same 失效
标题翻译：行地址解码器和具有其的半导体存储器件
公开(公告)号：US08072835B2
公开(公告)日：2011-12-06
申请号：US12344841
申请日：2008-12-29
申请人： Gyung Tae Kim
发明人： Gyung Tae Kim
IPC分类号： G11C8/00
CPC分类号： G11C11/4087 , G11C8/08 , G11C8/14 , G11C8/20 , G11C29/18 , G11C2029/1202 , G11C2029/1802 , G11C2029/2602
摘要： A row address decoder includes a first main word line decoding unit decoding first and second row addresses to generate first to fourth main decoding signals. When a data storage test is performed, the first to fourth main decoding signals are enabled at first to fourth timings, respectively. The row address decoder also includes a second main word line decoding unit decoding third and fourth row addresses to generate fifth to eighth main decoding signals. When a data storage test is performed, the fifth to eight main decoding signals are enabled at first to fourth timings, respectively. A main word line enable signal generating unit decodes the first to fourth main decoding signals and the fifth to eighth main decoding signals to generate first to sixteenth main word line enable signals that are enabled at different times.
摘要翻译：行地址解码器包括第一主字线解码单元，用于对第一和第二行地址进行解码，以产生第一至第四主解码信号。当执行数据存储测试时，第一至第四主解码信号分别在第一至第四定时被使能。行地址解码器还包括第二主字线解码单元，用于解码第三和第四行地址以产生第五至第八主解码信号。当执行数据存储测试时，分别在第一到第四定时使能第五到八个主解码信号。主字符串使能信号产生单元对第一至第四主要解码信号和第五至第八主要解码信号进行解码，以产生在不同时间使能的第一至第十六主要字线使能信号。

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