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1. 发明授权

US08547752B2 Method of reading data in non-volatile memory device, and device thereof 失效
标题翻译：在非易失性存储装置中读取数据的方法及其装置
公开(公告)号：US08547752B2
公开(公告)日：2013-10-01
申请号：US13198750
申请日：2011-08-05
申请人： Hee Seok Eun , Jae Hong Kim , Kyoung Lae Cho
发明人： Hee Seok Eun , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G11C11/34
CPC分类号： G11C11/5628 , G11C16/26 , G11C16/3418
摘要： A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.
摘要翻译：一种在非易失性存储器件中读取数据的方法。该方法包括使用第一读取级别读取存储单元阵列中的第一页的多个存储单元，使用第二读取级别读取与第一页的存储单元相邻的第二页的多个存储单元，确定基于第一读取电平来改变第一页面的每个存储器单元的状态，以基于第二读取电平来验证第二页的每个存储单元的阈值电压，并且修改第二页的每个存储器单元的状态第二页根据确定的结果。

2. 发明申请

US20120033502A1 METHOD OF READING DATA IN NON-VOLATILE MEMORY DEVICE, AND DEVICE THEREOF 失效
标题翻译：在非易失性存储器件中读取数据的方法及其装置
公开(公告)号：US20120033502A1
公开(公告)日：2012-02-09
申请号：US13198750
申请日：2011-08-05
申请人： Hee Seok EUN , Jae Hong Kim , Kyoung Lae Cho
发明人： Hee Seok EUN , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G11C16/26 , G11C16/06
CPC分类号： G11C11/5628 , G11C16/26 , G11C16/3418
摘要： A method of reading data in a non-volatile memory device. The method includes reading a plurality of memory cells of a first page in a memory cell array using a first read level, reading a plurality of memory cells of a second page adjacent to the memory cells of the first page using a second read level, determining whether a state of each memory cell of the first page has been changed based on the first read level to verify a threshold voltage of each memory cell of the second page based on the second read level, and revising the state of each memory cell of the second page according to a result of the determination.
摘要翻译：一种在非易失性存储器件中读取数据的方法。该方法包括使用第一读取级别读取存储单元阵列中的第一页的多个存储单元，使用第二读取级别读取与第一页的存储单元相邻的第二页的多个存储单元，确定基于第一读取电平来改变第一页面的每个存储器单元的状态，以基于第二读取电平来验证第二页的每个存储单元的阈值电压，并且修改第二页的每个存储器单元的状态第二页根据确定的结果。

3. 发明授权

US08473668B2 Memory device and wear leveling method 有权
标题翻译：记忆装置和磨损均衡方法
公开(公告)号：US08473668B2
公开(公告)日：2013-06-25
申请号：US12379273
申请日：2009-02-18
申请人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong
IPC分类号： G06F12/00
CPC分类号： G11C16/349 , G11C11/5628 , G11C2211/5644
摘要： The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.
摘要翻译：存储装置基于第一存储单元的擦除次数，第一存储单元被擦除后的经过时间，第二存储单元的次数，选择第一存储单元和第二存储单元中的任一个，被擦除，并且第二存储单元被擦除之后的经过时间，以及所选存储单元中的程序数据。存储器件可以改善存储器单元的阈值电压分布和存储单元的耐久性。

4. 发明授权

US08279668B2 Apparatus and method of memory programming 有权
标题翻译：存储器编程的装置和方法
公开(公告)号：US08279668B2
公开(公告)日：2012-10-02
申请号：US12801532
申请日：2010-06-14
申请人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
发明人： Kyoung Lae Cho , Yoon Dong Park , Jun Jin Kong , Jong Han Kim , Jae Hong Kim , Young Hwan Lee , Heeseok Eun , Seung-Hwan Song
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C29/00 , G11C2216/14
摘要： A memory programming apparatuses and/or methods are provided. The memory programming apparatus may include a data storage unit, a first counting unit, an index storage unit and/or a programming unit. The data storage unit may be configured to store a data page. The first counting unit may be configured to generate index information by counting a number of cells included in at least one reference threshold voltage state based on the data page. The index storage unit may be configured to store, the generated index information. The programming unit may be configured to store the data page in the data storage unit and store the generated index information in the index storage unit. The first counting unit may send the generated index information to the programming unit. The memory programming apparatus can monitor distribution states of threshold voltages in memory cells.
摘要翻译：提供了存储器编程设备和/或方法。存储器编程装置可以包括数据存储单元，第一计数单元，索引存储单元和/或编程单元。数据存储单元可以被配置为存储数据页。第一计数单元可以被配置为通过基于数据页计数包括在至少一个参考阈值电压状态中的单元的数量来生成索引信息。索引存储单元可以被配置为存储所生成的索引信息。编程单元可以被配置为将数据页存储在数据存储单元中，并将生成的索引信息存储在索引存储单元中。第一计数单元可以将生成的索引信息发送到编程单元。存储器编程装置可以监视存储器单元中阈值电压的分布状态。

5. 发明授权

US08276046B2 Apparatus for determining number of bits to be stored in memory cell 失效
标题翻译：用于确定要存储在存储单元中的位数的装置
公开(公告)号：US08276046B2
公开(公告)日：2012-09-25
申请号：US12219103
申请日：2008-07-16
申请人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
发明人： Seung-Hwan Song , Kyoung Lae Cho , Jun Jin Kong , Jae Hong Kim
IPC分类号： H03M13/00
CPC分类号： G11C11/56 , G06F11/1012 , G11C29/00
摘要： Example embodiments relate to an apparatus which may determine a length of data to be stored in a memory cell, and may store the data in a memory based on the determined length. A memory data storage apparatus according to example embodiments may, include: a determination unit that may determine a number of bits of data and a number of bits of data detection information to be stored in a memory cell; a data receiving unit that may receive data corresponding to the determined number of bits; an error correction coding unit that may perform an error correction coding with respect to the received data and generate data detection information corresponding to the number of bits of the data detection information; and a data storage unit that may store the received data and generated data detection information in the memory cell.
摘要翻译：示例性实施例涉及可以确定要存储在存储器单元中的数据的长度的装置，并且可以基于所确定的长度将数据存储在存储器中。根据示例实施例的存储器数据存储装置可以包括：确定单元，其可以确定要存储在存储器单元中的数据的位数和数据检测信息的位数; 数据接收单元，其可以接收与所确定的位数相对应的数据; 纠错编码单元，其可以对所接收的数据执行纠错编码，并生成与数据检测信息的位数相对应的数据检测信息; 以及数据存储单元，其可以将所接收的数据和生成的数据检测信息存储在存储单元中。

6. 发明申请

US20100027342A1 Memory device and memory data determination method 有权
标题翻译：存储器和存储器数据确定方法
公开(公告)号：US20100027342A1
公开(公告)日：2010-02-04
申请号：US12461060
申请日：2009-07-30
申请人： Heeseok Eun , Jae Hong Kim , Kyoung Lae Cho
发明人： Heeseok Eun , Jae Hong Kim , Kyoung Lae Cho
IPC分类号： G11C16/04
CPC分类号： G11C16/10 , G11C11/5642 , G11C16/3418 , G11C16/3427
摘要： A memory device and a memory data determination method are provided. The memory device may estimate a threshold voltage shift of a first memory cell based on data before the first memory cell is programmed and a target program threshold voltage of the first memory cell. The memory device may generate a metric of a threshold voltage shift of a second memory cell based on the estimated threshold voltage shift of the first memory cell. Also, the memory device may determine data stored in the second memory cell based on the metric.
摘要翻译：提供存储器件和存储器数据确定方法。存储器件可以基于第一存储器单元被编程之前的数据和第一存储器单元的目标程序阈值电压来估计第一存储器单元的阈值电压偏移。存储器件可以基于第一存储器单元的估计的阈值电压偏移来产生第二存储器单元的阈值电压偏移的度量。此外，存储器设备可以基于度量来确定存储在第二存储器单元中的数据。

7. 发明申请

US20100027335A1 Memory device and wear leveling method 有权
标题翻译：记忆装置和磨损均衡方法
公开(公告)号：US20100027335A1
公开(公告)日：2010-02-04
申请号：US12379273
申请日：2009-02-18
申请人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong
发明人： Yong June Kim , Jae Hong Kim , Kyoung Lae Cho , Jun Jin Kong
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/349 , G11C11/5628 , G11C2211/5644
摘要： The memory device selects any one of a first memory cell and a second memory cell based on a number of times that the first memory cell is erased, an elapsed time after the first memory cell is erased, a number of times that the second memory cell is erased, and an elapsed time after the second memory cell is erased, and program data in the selected memory cell. The memory device may improve distribution of threshold voltage of memory cells and endurance of the memory cells.
摘要翻译：存储装置基于第一存储单元的擦除次数，第一存储单元被擦除后的经过时间，第二存储单元的次数，选择第一存储单元和第二存储单元中的任一个，被擦除，并且第二存储单元被擦除之后的经过时间，以及所选存储单元中的程序数据。存储器件可以改善存储器单元的阈值电压分布和存储单元的耐久性。

8. 发明申请

US20090282319A1 HIERARCHICAL DECODING APPARATUS 有权
标题翻译：分层解码设备
公开(公告)号：US20090282319A1
公开(公告)日：2009-11-12
申请号：US12428511
申请日：2009-04-23
申请人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
发明人： Jong Seon No , Beom Kyu Shin , Seok Il Youn , Jae Dong Yang , Jun Jin Kong , Jae Hong Kim , Yong June Kim , Kyoung Lae Cho
IPC分类号： H03M13/15 , G06F11/10 , H03M13/45
CPC分类号： H03M13/2906 , H03M13/1102 , H03M13/1108 , H03M13/1111 , H03M13/1117 , H03M13/1194 , H03M13/136 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/296 , H03M13/3707 , H03M13/3738
摘要： A decoder includes multiple decoder stages and a controller. The decoder stages perform decoding operations with respect to a received signal using corresponding different decoding algorithms. The controller determines whether the decoding operation performed by one of the decoder stages with respect to the received signal is successful, and controls the decoding operation of each of the other decoder stages in response to a result of the determination.
摘要翻译：解码器包括多个解码器级和控制器。解码器级使用相应的不同解码算法对接收到的信号执行解码操作。控制器确定解码器中的一个相对于接收信号执行的解码操作是否成功，并且响应于确定的结果来控制每个其他解码器级的解码操作。

9. 发明申请

US20090210776A1 Memory device and memory data reading method 有权
标题翻译：存储器和存储器数据读取方式
公开(公告)号：US20090210776A1
公开(公告)日：2009-08-20
申请号：US12216744
申请日：2008-07-10
申请人： Kyoung Lae Cho , Jae Hong Kim , Yoon Dong Park , Jun Jin Kong , Dong Hyuk Chae
发明人： Kyoung Lae Cho , Jae Hong Kim , Yoon Dong Park , Jun Jin Kong , Dong Hyuk Chae
IPC分类号： H03M13/09 , G06F11/10
CPC分类号： G06F11/1072 , H03M13/09 , H03M13/15 , H03M13/1515 , H03M13/152
摘要： Example embodiments may provide a memory device and memory data reading method. The memory device according to example embodiments may include a multi-bit cell array, an error detector which may read a first data page from a memory page in the multi-bit cell array and may detect an error-bit of the first data page, and an estimator which may identify a multi-bit cell where the error-bit is stored and may estimate data stored in the identified multi-bit cell among data of a second data page. Therefore, the memory device and memory data reading method may have an effect of reducing an error when reading data stored in the multi-bit cell and monitoring a state of the multi-bit cell without additional overhead.
摘要翻译：示例性实施例可以提供存储器件和存储器数据读取方法。根据示例实施例的存储器件可以包括多位单元阵列，错误检测器，其可以从多位单元阵列中的存储器页读取第一数据页，并且可以检测第一数据页的错误位，以及估计器，其可以识别存储错误位的多位单元，并且可以估计存储在所识别的多位单元中的数据在第二数据页的数据中。因此，存储器件和存储器数据读取方法可以具有当读取存储在多位单元中的数据并且监视多位单元的状态而没有额外开销时减小误差的效果。

10. 发明授权

US08972775B2 Memory device and method of managing memory data error including determining verification voltages and changing threshold voltages based on a corrected error bit 有权
标题翻译：存储器件和管理存储器数据错误的方法，包括基于校正的误差位确定验证电压和改变阈值电压
公开(公告)号：US08972775B2
公开(公告)日：2015-03-03
申请号：US12453163
申请日：2009-04-30
申请人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
发明人： Yong June Kim , Jae Hong Kim , Jun Jin Kong , Kyoung Lae Cho
IPC分类号： G06F11/07 , G11C16/10 , G06F11/10 , G11C11/56 , G11C16/34 , G11C29/00
CPC分类号： G11C16/10 , G06F11/1072 , G11C11/5628 , G11C11/5642 , G11C16/3454 , G11C29/00 , G11C2211/5621 , G11C2211/5634
摘要： Memory devices and/or methods of managing memory data errors are provided. A memory device detects and corrects an error bit of data read from a plurality of memory cells, and identifies a memory cell storing the detected error bit. The memory device assigns a verification voltage to each of the plurality of first memory cells, the assigned verification voltage corresponding to the corrected bit for the identified memory cell, the assigned verification voltage corresponding to the read data for the remaining memory cells. The memory device readjusts the data stored in the plurality of memory cells using the assigned verification voltage. Through this, it is possible to increase a retention period of the data of the memory device.
摘要翻译：提供了存储器件和/或管理存储器数据错误的方法。存储器件检测并校正从多个存储器单元读取的数据的错误位，并且识别存储检测到的错误位的存储单元。存储装置向多个第一存储器单元中的每一个分配验证电压，对应于所识别的存储单元的校正位的分配的验证电压，对应于剩余存储单元的读取数据的分配验证电压。存储装置使用分配的验证电压重新调整存储在多个存储单元中的数据。由此，可以增加存储装置的数据的保持期。

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