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1. 发明申请

US20060202255A1 Split gate non-volatile memory devices and methods of forming same 失效
公开(公告)号：US20060202255A1
公开(公告)日：2006-09-14
申请号：US11368154
申请日：2006-03-03
申请人： Hee Jeon , Sung-Taeg Kang , Hyok-Ki Kwon , Yong Kim , BoYoung Seo , Seung Yoon , Jeong-Uk Han
发明人： Hee Jeon , Sung-Taeg Kang , Hyok-Ki Kwon , Yong Kim , BoYoung Seo , Seung Yoon , Jeong-Uk Han
IPC分类号： H01L29/788 , H01L21/8238
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.

2. 发明申请

US20060199336A1 Split gate non-volatile memory devices and methods of forming same 失效
标题翻译：分闸非易失性存储器件及其形成方法
公开(公告)号：US20060199336A1
公开(公告)日：2006-09-07
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

3. 发明申请

US20080093647A1 SPLIT GATE NON-VOLATILE MEMORY DEVICES AND METHODS OF FORMING THE SAME 失效
标题翻译：分离栅非易失性存储器件及其形成方法
公开(公告)号：US20080093647A1
公开(公告)日：2008-04-24
申请号：US11957037
申请日：2007-12-14
申请人： Sung-Taeg KANG , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg KANG , Hyok-Ki Kwon , Bo Seo , Seung Yoon , Hee Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L29/788
CPC分类号： H01L29/7887 , H01L29/66825
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

4. 发明授权

US07315057B2 Split gate non-volatile memory devices and methods of forming same 失效
标题翻译：分闸非易失性存储器件及其形成方法
公开(公告)号：US07315057B2
公开(公告)日：2008-01-01
申请号：US11368154
申请日：2006-03-03
申请人： Hee Seog Jeon , Sung-Taeg Kang , Hyok-Ki Kwon , Yong Tae Kim , BoYoung Seo , Seung Beom Yoon , Jeong-Uk Han
发明人： Hee Seog Jeon , Sung-Taeg Kang , Hyok-Ki Kwon , Yong Tae Kim , BoYoung Seo , Seung Beom Yoon , Jeong-Uk Han
IPC分类号： H01L29/788 , H01L21/336
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/115 , H01L29/42328 , H01L29/7885
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

5. 发明授权

US07602008B2 Split gate non-volatile memory devices and methods of forming the same 失效
标题翻译：分闸非易失性存储器件及其形成方法
公开(公告)号：US07602008B2
公开(公告)日：2009-10-13
申请号：US11957037
申请日：2007-12-14
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L27/115
CPC分类号： H01L29/7887 , H01L29/66825
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

6. 发明申请

US20070045673A1 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20070045673A1
公开(公告)日：2007-03-01
申请号：US11488911
申请日：2006-07-18
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
IPC分类号： G11C11/34
CPC分类号： H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.
摘要翻译：非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。单元栅极图案和选择线之间的距离小于选择线的宽度。

7. 发明授权

US07553725B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07553725B2
公开(公告)日：2009-06-30
申请号：US11488911
申请日：2006-07-18
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.
摘要翻译：非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。单元栅极图案和选择线之间的距离小于选择线的宽度。

8. 发明授权

US07320913B2 Methods of forming split-gate non-volatile memory devices 失效
标题翻译：形成分闸非易失性存储器件的方法
公开(公告)号：US07320913B2
公开(公告)日：2008-01-22
申请号：US11368247
申请日：2006-03-03
申请人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
发明人： Sung-Taeg Kang , Hyok-Ki Kwon , Bo Young Seo , Seung Beom Yoon , Hee Seog Jeon , Yong-Suk Choi , Jeong-Uk Han
IPC分类号： H01L21/336
CPC分类号： H01L29/7885 , G11C16/0425 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/42328
摘要： Non-volatile memory devices and methods for fabricating non-volatile memory devices are disclosed. More specifically, split gate memory devices are provided having frameworks that provide increased floating gate coupling ratios, thereby enabling enhanced programming and erasing efficiency and performance.
摘要翻译：公开了用于制造非易失性存储器件的非易失性存储器件和方法。更具体地，提供具有提供增加的浮栅耦合比的框架的分割门存储器件，从而实现增强的编程和擦除效率和性能。

9. 发明授权

US07531410B2 Semiconductor flash memory device and method of fabricating the same 失效
标题翻译：半导体闪存器件及其制造方法
公开(公告)号：US07531410B2
公开(公告)日：2009-05-12
申请号：US11648057
申请日：2006-12-29
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42336
摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.
摘要翻译：半导体闪存器件。闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。栅极绝缘膜介于浮栅电极和半导体衬底之间。控制栅电极设置在浮栅电极上。浮栅电极包括与凹部的倾斜侧相邻的突起。

10. 发明申请

US20070278531A1 Semiconductor flash memory device and method of fabricating the same 失效
标题翻译：半导体闪存器件及其制造方法
公开(公告)号：US20070278531A1
公开(公告)日：2007-12-06
申请号：US11648057
申请日：2006-12-29
申请人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
发明人： Yong-Suk Choi , Jeong-Uk Han , Hee-Seog Jeon , Seung-Jin Yang , Hyok-Ki Kwon
IPC分类号： H01L29/76
CPC分类号： H01L29/7881 , H01L21/28273 , H01L29/42336
摘要： A semiconductor flash memory device. The flash memory device includes a floating gate electrode disposed in a recess having slanted sides in a semiconductor substrate. A gate insulation film is interposed between the floating gate electrode and the semiconductor substrate. A control gate electrode is disposed over the floating gate electrode. The floating gate electrode includes projections adjacent to the slanted sides of the recess.
摘要翻译：半导体闪存器件。闪存器件包括设置在具有在半导体衬底中的倾斜侧面的凹部中的浮栅电极。栅极绝缘膜介于浮栅电极和半导体衬底之间。控制栅电极设置在浮栅电极上。浮栅电极包括与凹部的倾斜侧相邻的突起。

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