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1. 发明授权

US08174884B2 Low power, single poly EEPROM cell with voltage divider 有权
公开(公告)号：US08174884B2
公开(公告)日：2012-05-08
申请号：US12804395
申请日：2010-07-20
申请人： Harvey J. Stiegler , Allan T. Mitchell , Robert N. Rountree
发明人： Harvey J. Stiegler , Allan T. Mitchell , Robert N. Rountree
IPC分类号： G11C11/34
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).

2. 发明申请

US20120020162A1 Low power, single poly EEPROM cell with voltage divider 有权
标题翻译：低功耗，单分辨率多层EEPROM单元，带分压器
公开(公告)号：US20120020162A1
公开(公告)日：2012-01-26
申请号：US12804395
申请日：2010-07-20
申请人： Harvey J. Stiegler , Allan T. Mitchell , Robert N. Rountree
发明人： Harvey J. Stiegler , Allan T. Mitchell , Robert N. Rountree
IPC分类号： G11C16/04 , H03F3/45
CPC分类号： G11C16/0441
摘要： An Electrically Erasable Programmable Read Only Memory (EEPROM) memory array (FIGS. 7 and 8) is disclosed. The memory array includes a plurality of memory cells arranged in rows and columns. Each memory cell has a switch (806) coupled to receive a first program voltage (PGMDATA) and a first select signal (ROWSEL). A voltage divider (804) is coupled in series with the switch. A sense transistor (152) has a sense control terminal (156) and a current path coupled between an output terminal (108) and a reference terminal (110). A first capacitor (154) has a first terminal coupled to the switch and a second terminal coupled to the sense control terminal. An access transistor (716) has a control terminal coupled to receive a read signal (721), and a current path coupled between the output terminal and a bit line (718).
摘要翻译：公开了一种电可擦除可编程只读存储器（EEPROM）存储器阵列（图7和8）。存储器阵列包括以行和列排列的多个存储单元。每个存储单元具有耦合以接收第一编程电压（PGMDATA）和第一选择信号（ROWSEL）的开关（806）。分压器（804）与开关串联耦合。感测晶体管（152）具有感测控制端子（156）和耦合在输出端子（108）和参考端子（110）之间的电流通路。第一电容器（154）具有耦合到开关的第一端子和耦合到感测控制端子的第二端子。存取晶体管（716）具有耦合以接收读取信号（721）的控制端和耦合在输出端和位线（718）之间的电流通路。

3. 发明申请

US20130120056A1 POWER SUPPLY PROTECTION CIRCUIT AND METHOD 有权
标题翻译：电源保护电路及方法
公开(公告)号：US20130120056A1
公开(公告)日：2013-05-16
申请号：US13609005
申请日：2012-09-10
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： G05F3/02
CPC分类号： G06F1/28 , G06F1/30 , G11C5/005 , H02M3/07
摘要： A method of protecting a power supply voltage in an integrated circuit is disclosed. The method includes storing charge in a charge reservoir capacitor (142), receiving a power supply sample voltage (140), and receiving a load power supply voltage (VDDL, 102). The power supply sample voltage is compared to the load power supply voltage (150). Charge is added from the charge reservoir capacitor (142) to the load power supply (VDDL) through transistor 126 and capacitor 144 in response to the step of comparing.
摘要翻译：公开了一种保护集成电路中的电源电压的方法。该方法包括将电荷存储在电荷储存电容器（142）中，接收电源采样电压（140），并接收负载电源电压（VDDL，102）。将电源采样电压与负载电源电压（150）进行比较。响应于比较步骤，通过晶体管126和电容器144从充电储存电容器（142）向负载电源（VDDL）充电。

4. 发明授权

US5808482A Row decoder with level translator 失效
标题翻译：行解码器与电平转换器
公开(公告)号：US5808482A
公开(公告)日：1998-09-15
申请号：US816860
申请日：1997-03-13
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： G11C8/10 , H03K19/0185 , G11C8/00
CPC分类号： G11C8/10 , H03K19/018521
摘要： A combined row decoder and level translator powered by an on-chip high voltage supply results in an efficient layout, area savings and elimination of the global precharge signal resulting in additional area and power savings. In addition, power from the high voltage supply is consumed only by the level translator and wordline driver of the selected decoder resulting in additional power savings.
摘要翻译：由片内高压电源供电的组合行解码器和电平转换器可实现有效的布局，面积节省和全局预充电信号的消除，从而实现额外的面积和功耗节省。此外，来自高压电源的功率仅由所选解码器的电平转换器和字线驱动器消耗，导致额外的功率节省。

5. 发明授权

US5424977A Sense amplifier having shared dummy cell 失效
标题翻译：具有共享虚拟单元的感应放大器
公开(公告)号：US5424977A
公开(公告)日：1995-06-13
申请号：US121112
申请日：1993-09-13
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： G11C7/14 , G11C11/4099 , G11C11/00 , G11C7/00
CPC分类号： G11C7/14 , G11C11/4099
摘要： The present invention describes a circuit and method for utilizing a single dummy cell for each sense amplifier in a dynamic random access memory (DRAM) device. A precharge transistor connects a dummy cell capacitor to a reference potential and decoded selection transistors. The use of decoded selection transistors provides a means to share the dummy cell capacitor between either input of a differential or sense amplifier thereby reducing required area and circuit complexity.
摘要翻译：本发明描述了一种用于在动态随机存取存储器（DRAM）设备中为每个读出放大器利用单个虚拟单元的电路和方法。预充电晶体管将虚拟单元电容器连接到参考电位和解码的选择晶体管。使用解码的选择晶体管提供了在差分或读出放大器的任一输入端之间共享虚设单元电容器的方法，从而减少所需面积和电路复杂度。

6. 发明授权

US4939616A Circuit structure with enhanced electrostatic discharge protection 失效
标题翻译：具有增强静电放电保护的电路结构
公开(公告)号：US4939616A
公开(公告)日：1990-07-03
申请号：US434592
申请日：1989-11-13
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： H01L27/02
CPC分类号： H01L27/0251 , H01L29/0626 , H01L29/87
摘要： The described embodiments of the present invention provide an input protection device with a low trigger threshold. The structure is a silicon controlled rectifier (SCR) type of device wherein the triggering mechanism is avalanche conduction at the interface between the N-well surrounding a portion of the protection device and the P-type substrate. The embodiments provide a lowered threshold voltage by providing a highly doped region of the same conductivity type as the well at the interface between the well and the substrate. This highly doped region is connected to a resistor which is then connected to the protected node. The resistor and heavily doped region at the intersection between the N-well and substrate provides an additional source of current for avalanching at a lower voltage. Thus the trigger voltage of the protection system is substantially lowered. In other embodiments of the present invention an additional source of triggering current is provided by an N+ contact region in the N-well which is close to the interface between the N-well and the P substrate adjacent to the area closest to the N+ emitter of the silicon controlled device. Either of these highly doped charge injection regions may be fed by resistors fabricated with the heavily doped regions themselves or may utilize the N-well itself as a resistive element.
摘要翻译：本发明的所描述的实施例提供了具有低触发阈值的输入保护装置。该结构是可控硅整流器（SCR）类型的器件，其中触发机构在围绕保护器件的一部分的N阱和P型衬底之间的界面处是雪崩导电。实施例通过在阱和衬底之间的界面处提供与阱相同的导电类型的高掺杂区域来提供降低的阈值电压。该高掺杂区域连接到电阻器，然后电阻器连接到受保护的节点。在N阱和衬底之间的交叉处的电阻器和重掺杂区域提供了额外的电流源，用于在较低电压下进行雪崩。因此，保护系统的触发电压显着降低。在本发明的其他实施例中，附加的触发电流源由N阱中的N +接触区域提供，其接近N阱和P衬底之间的界面，邻近于最接近N +发射极的区域硅控制器件。这些高度掺杂的电荷注入区域中的任何一个可以由用重掺杂区域本身制造的电阻馈送，或者可以利用N阱本身作为电阻元件。

7. 发明申请

US20150021659A1 PROGRAMMABLE SCR FOR ESD PROTECTION 有权
标题翻译：用于ESD保护的可编程SCR
公开(公告)号：US20150021659A1
公开(公告)日：2015-01-22
申请号：US14509963
申请日：2014-10-08
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： H01L29/735 , H01L29/73 , H01L27/02
CPC分类号： H01L29/735 , H01L21/82 , H01L27/0262 , H01L27/04 , H01L29/7302 , H01L29/7436
摘要： A programmable semiconductor controlled rectifier (SCR) circuit is disclosed. The SCR includes a first terminal (310) and a second terminal (308). A first lightly doped region (304) having a first conductivity type (N−) is formed on a second lightly doped region (314) having a second conductivity type (P−). A first heavily doped region having the second conductivity type (P+) is formed within the first lightly doped region at a face of the substrate and coupled to the first terminal. A second heavily doped region having the first conductivity type (N+) is formed within the second lightly doped region at the face of the substrate and coupled to the second terminal. A third heavily doped region (400) having the second conductivity type (P+) is formed at the face of the substrate between the first and second heavily doped regions and electrically connected to the second lightly doped region. A first transistor (316) having a control terminal and having a first current path terminal coupled to the third heavily doped region and a second current path terminal coupled to the second terminal is arranged to control a holding voltage of the circuit.
摘要翻译：公开了可编程半导体可控整流器（SCR）电路。 SCR包括第一端子（310）和第二端子（308）。在具有第二导电类型（P-）的第二轻掺杂区域（314）上形成具有第一导电类型（N-）的第一轻掺杂区域（304）。具有第二导电类型（P +）的第一重掺杂区域形成在衬底的第一轻掺杂区域内并耦合到第一端子。具有第一导电类型（N +）的第二重掺杂区域形成在衬底的第二轻掺杂区域内并耦合到第二端子。在第一和第二重掺杂区域之间的衬底的表面处形成具有第二导电类型（P +）的第三重掺杂区域（400），并电连接到第二轻掺杂区域。具有控制端子并具有耦合到第三重掺杂区域的第一电流通路端子和耦合到第二端子的第二电流通路端子的第一晶体管（316）布置成控制电路的保持电压。

8. 发明授权

US08625377B2 Low voltage efuse programming circuit and method 有权
标题翻译：低压efuse编程电路及方法
公开(公告)号：US08625377B2
公开(公告)日：2014-01-07
申请号：US13763583
申请日：2013-02-08
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： G11C17/18
CPC分类号： G11C17/16 , G11C7/00 , G11C17/18
摘要： A circuit for programming a fuse is disclosed. The circuit includes a voltage supply terminal (Vf) and a semiconductor controlled rectifier (222, 224). The fuse is coupled between the voltage supply terminal and the semiconductor controlled rectifier. A switching circuit (200, 202, 208, 210) is coupled to the semiconductor controlled rectifier.
摘要翻译：公开了一种用于编程保险丝的电路。电路包括电压源端子（Vf）和半导体可控整流器（222,224）。保险丝耦合在电源端和半导体可控整流器之间。开关电路（200,202,208,210）耦合到半导体可控整流器。

9. 发明授权

US6016876A Weed extractor 失效
标题翻译：杂草提取器
公开(公告)号：US6016876A
公开(公告)日：2000-01-25
申请号：US149429
申请日：1998-09-08
申请人： Barbara P. Rountree , Robert N. Rountree
发明人： Barbara P. Rountree , Robert N. Rountree
IPC分类号： A01B1/18
CPC分类号： A01B1/18
摘要： A weed extractor is designed with a shaft (100) having a handle end and a distal end. A foot piece (116) has a first end and a second end. The first end is slidely attached to the shaft proximal to the distal end. The foot piece extends laterally from the shaft. A bit assembly (118) has a plurality of pivotally mounted opposed spikes. The bit assembly has an open position and a closed position, and moves between the open position and the closed position in response to movement of the foot piece with respect to the shaft. At least two opposed spikes are spaced apart from a plane bisecting an angle between the at least two opposed spikes in the open position. A part of each of the at least two opposed spikes intersects the plane in the closed position.
摘要翻译：杂草提取器设计有具有手柄端和远端的轴（100）。脚件（116）具有第一端和第二端。第一端滑动地附接到靠近远端的轴。脚部从轴向横向延伸。有点组件（118）具有多个可枢转地安装的相对的钉。钻头组件具有打开位置和关闭位置，并且响应于脚件相对于轴的移动而在打开位置和关闭位置之间移动。至少两个相对的钉与在打开位置中将至少两个相对的尖峰之间的角度平分的平面间隔开。所述至少两个相对的尖峰中的每一个的一部分在所述关闭位置与所述平面相交。

10. 发明授权

US5682110A Low capacitance bus driver 失效
标题翻译：低电容总线驱动
公开(公告)号：US5682110A
公开(公告)日：1997-10-28
申请号：US855958
申请日：1992-03-23
申请人： Robert N. Rountree
发明人： Robert N. Rountree
IPC分类号： H03K19/094 , H03K19/084
CPC分类号： H03K19/09429
摘要： A low capacitance bus driver circuit includes, in this example, P-channel and N-channel output transistors with input gates connected by means of CMOS pass gates to a common input terminal and having respective P-channel and N-channel transistors connected to the input gates of the output transistors so as to place them in a high impedance state when the CMOS pass gates are disabled. Input capacitance of the bus driver circuit is greatly reduced by elimination of CMOS gate capacitance when the bus driver is enabled. When the bus driver is not enabled, it provides optimal performance of a single gate delay from input to output without the need for series connected output devices or correspondingly higher input capacitance.
摘要翻译：低电容总线驱动器电路在本例中包括P沟道和N沟道输出晶体管，其输入栅极通过CMOS栅极连接到公共输入端并且具有连接到第二栅极的相应P沟道和N沟道晶体管输入晶体管的输入栅极，以便当CMOS通道禁止时将它们置于高阻抗状态。当总线驱动器使能时，通过消除CMOS栅极电容，可大大减少总线驱动电路的输入电容。当总线驱动器未使能时，它提供从输入到输出的单个门延迟的最佳性能，而不需要串联连接的输出设备或相应较高的输入电容。

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