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    • 5. 发明授权
    • Analog switch circuit
    • 模拟开关电路
    • US5880621A
    • 1999-03-09
    • US904341
    • 1997-07-31
    • Ikuo Ohashi
    • Ikuo Ohashi
    • H01L27/06H01L21/8249H03K17/16H03K17/687H03K3/01
    • H03K17/162
    • Disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; first and second diodes which are in parallel and reversely to each other connected between a back gate of the first transistor and a high-potential power source; and third and fourth diodes which are in parallel and reversely to each other connected between a back gate of the second transistor and a low-potential power source. Further disclosed is an analog switch circuit which has: an analog switch which is composed of a P-channel first transistor and a N-channel second transistor whose drains are connected to each other and whose sources are connected to each other; and a N-channel third transistor whose gate is connected to a high-potential power source and/or a P-channel fourth transistor whose gate is connected to a low-potential power source; wherein the third transistor and/or the fourth transistor are/is in series connected between an input terminal and an input terminal of the analog switch.
    • 公开了一种模拟开关电路,其具有:模拟开关,其由P沟道第一晶体管和N沟道第二晶体管组成,漏极彼此连接并且源极彼此连接; 彼此并联并相反地连接在第一晶体管的背栅极和高电位电源之间的第一和第二二极管; 并且彼此并联并相反地连接在第二晶体管的背栅极和低电位电源之间的第三和第四二极管。 还公开了一种模拟开关电路,其具有:由P沟道第一晶体管和N沟道第二晶体管组成的模拟开关,漏极彼此连接并且源极彼此连接; 以及N沟道第三晶体管,其栅极连接到高电位电源和/或栅极连接到低电位电源的P沟道第四晶体管; 其中第三晶体管和/或第四晶体管串联连接在模拟开关的输入端和输入端之间。
    • 7. 发明授权
    • Semiconductor device having power MOS transistor including parasitic
transistor
    • 具有功率MOS晶体管的半导体器件包括寄生晶体管
    • US5912496A
    • 1999-06-15
    • US795630
    • 1997-02-06
    • Ikuo Ohashi
    • Ikuo Ohashi
    • H01L21/822H01L21/8238H01L27/02H01L27/04H01L27/092H03K17/08H01L23/62
    • H01L27/0251H01L2924/0002
    • A semiconductor device has a power MOSFET 12 connected between a semiconductor substrate 21 of N-type as an output terminal 15 and a GND terminal 16 connected to a first semiconductor layer 22 formed on the semiconductor substrate 21 and having a gate connected to a first node for controlling the supply of electric current to a load connected between the GND terminal and the output terminal, a control circuit receiving an input signal and controlling an operation of the power MOSFET in response to the input signal, an input terminal provided in a second semiconductor layer 23 of N-type formed on the first semiconductor layer 22, a parasitic transistor 24 connected between the semiconductor substrate and the second semiconductor layer, and having a base connected to the first semiconductor layer, and switching circuit for keeping the parasitic transistor at a non-conductive state.
    • 半导体器件具有连接在作为输出端子15的N型半导体衬底21和连接到形成在半导体衬底21上的第一半导体层22并且具有连接到第一节点的栅极的GND端子16之间的功率MOSFET 12 用于控制对连接在GND端子和输出端子之间的负载的电流的供应;控制电路,接收输入信号并根据输入信号控制功率MOSFET的工作;第二半导体 形成在第一半导体层22上的N型层23,连接在半导体衬底和第二半导体层之间并具有连接到第一半导体层的基极的寄生晶体管24,以及用于将寄生晶体管保持在第一半导体层 非导电状态。