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1. 发明授权

US06430682B1 Reliable branch predictions for real-time applications 有权
标题翻译：可靠的分支预测实时应用程序
公开(公告)号：US06430682B1
公开(公告)日：2002-08-06
申请号：US09151981
申请日：1998-09-11
申请人： Harry Dwyer, III
发明人： Harry Dwyer, III
IPC分类号： G06F932
CPC分类号： G06F9/30021 , G06F9/30094 , G06F9/3842 , G06F9/3844
摘要： Reliable branch predictions for real-time applications reduce both conditional branch execution time and uncertainties associated with their prediction in a computer implemented application. One method ensures that certain conditional branches are always correctly predicted, effectively converting them to jump instructions during program execution. Another method exploits the fact that some conditional branches always branch in the same direction within a task invocation, although that direction may vary across invocations. These methods improve computer processor utilization and performance.
摘要翻译：用于实时应用程序的可靠分支预测减少了在计算机实现的应用程序中与其预测相关的条件分支执行时间和不确定性。一种方法确保某些条件分支总是正确预测，在程序执行期间有效地将它们转换为跳转指令。另一种方法利用了一些事实，即一些条件分支总是在任务调用中以相同的方向分支，尽管该方向可能在调用之间变化。这些方法提高了计算机处理器的利用率和性能。

2. 发明授权

US5983335A Computer system having organization for multiple condition code setting and for testing instruction out-of-order 失效
标题翻译：计算机系统具有组合多条件代码设置和测试指令无序
公开(公告)号：US5983335A
公开(公告)日：1999-11-09
申请号：US841550
申请日：1997-04-30
申请人： Harry Dwyer, III
发明人： Harry Dwyer, III
IPC分类号： F02B75/02 , G06F9/38 , G06F11/34 , G06F15/00
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , F02B2075/027 , G06F11/3461
摘要： Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.
摘要翻译：具有适用于具有RISC组织的超标量处理器的具有多个无序指令发布系统的计算机系统还具有快速调度堆栈（FDS），动态指令调度系统，其可以发出多个无序指令每个循环到功能单元作为依赖允许。基本发布机制支持短周期时间，功能增强。条件代码相关的指令以多次和乱序发出。提出了快速注册重命名方案。指令压缩技术可实现快速精确中断和分支预测。一个或多个预测的条件分支指令之前和之后的指令可以发出乱序和同时发生。在错误预测的分支指令或导致精确中断的指令之后的执行指令的影响在一个机器周期中被撤消。

3. 发明授权

US5727167A Thresholding support in performance monitoring 失效
标题翻译：性能监控中的阈值支持
公开(公告)号：US5727167A
公开(公告)日：1998-03-10
申请号：US654068
申请日：1996-06-11
申请人： Harry Dwyer, III , Frank Eliot Levine , Edward Hugh Welbon , Charles Gordon Wright
发明人： Harry Dwyer, III , Frank Eliot Levine , Edward Hugh Welbon , Charles Gordon Wright
IPC分类号： G06F11/34 , G06F12/08 , G06F13/00
CPC分类号： G06F11/3419 , G06F11/3409 , G06F12/0802 , G06F2201/81 , G06F2201/86 , G06F2201/88 , G06F2201/885
摘要： A thresholding mechanism and method for performance monitoring of memory array access distribution times is disclosed. A data request signal sent to the memory hierarchy activates a first counter, having a first count value. A clock coupled to the first counter increments the first count value with each clock cycle, while also decrementing a decrementer having a predetermined threshold value. The first counter is deactivated by a completion signal when the data request is completed. A second counter having a second count value is incremented when the first count value is greater than the threshold value by the time the data request is complete.
摘要翻译：公开了一种用于存储器阵列访问分发时间的性能监视的阈值机制和方法。发送到存储器层级的数据请求信号激活具有第一计数值的第一计数器。耦合到第一计数器的时钟以每个时钟周期递增第一计数值，同时还递减具有预定阈值的减法器。当数据请求完成时，第一个计数器被完成信号禁用。当数据请求完成时，当第一计数值大于阈值时，具有第二计数值的第二计数器递增。

4. 发明授权

US06286027B1 Two step thread creation with register renaming 有权
标题翻译：两级线程创建与注册重命名
公开(公告)号：US06286027B1
公开(公告)日：2001-09-04
申请号：US09201034
申请日：1998-11-30
申请人： Harry Dwyer, III , Tor E. Jeremiassen , Hubert Rae McLellan, Jr.
发明人： Harry Dwyer, III , Tor E. Jeremiassen , Hubert Rae McLellan, Jr.
IPC分类号： G06F900
CPC分类号： G06F9/4843 , G06F9/384 , G06F9/3851
摘要： An apparatus and method in digital processing provides a simple and efficient way of communicating parameters from a parent thread to child thread with two step thread creation. The method comprising the steps of: allocating hardware context for the child thread; enabling the parent thread to execute other instructions wherein parent thread register writes update both parent and child architectural registers; and spawning the child thread. In essence, the parent thread sends parameters to the child by writing to the parent's registers prior to spawning of the child thread.
摘要翻译：数字处理中的装置和方法提供了一种简单而有效的方式，通过两步线程创建将参数从父线程传递到子线程。该方法包括以下步骤：为子线程分配硬件上下文; 使父线程执行其他指令，其中父线程寄存器写入更新父架构寄存器和子结构寄存器; 并产生子线程。实质上，父线程通过在生成子线程之前写入父进程的寄存器来向子进程发送参数。

5. 发明授权

US5881308A Computer organization for multiple and out-of-order execution of condition code testing and setting instructions out-of-order 失效
标题翻译：计算机组织用于多次和无序执行条件代码测试和设置指令无序
公开(公告)号：US5881308A
公开(公告)日：1999-03-09
申请号：US841549
申请日：1997-04-30
申请人： Harry Dwyer, III
发明人： Harry Dwyer, III
IPC分类号： F02B75/02 , G06F9/38 , G06F11/34
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , F02B2075/027 , G06F11/3461
摘要： Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.
摘要翻译：具有适用于具有RISC组织的超标量处理器的具有多个无序指令发布系统的计算机系统还具有快速调度堆栈（FDS），动态指令调度系统，其可以发出多个无序指令每个循环到功能单元作为依赖允许。基本发布机制支持短周期时间，功能增强。条件代码相关的指令以多次和乱序发出。提出了快速注册重命名方案。指令压缩技术可实现快速精确中断和分支预测。一个或多个预测的条件分支指令之前和之后的指令可以发出乱序和同时发生。在错误预测的分支指令或导致精确中断的指令之后的执行指令的影响在一个机器周期中被撤消。

6. 发明授权

US5996068A Method and apparatus for renaming registers corresponding to multiple thread identifications 失效
标题翻译：用于重命名对应于多个线程标识的寄存器的方法和装置
公开(公告)号：US5996068A
公开(公告)日：1999-11-30
申请号：US824599
申请日：1997-03-26
申请人： Harry Dwyer, III , Hubert Rae McLellan
发明人： Harry Dwyer, III , Hubert Rae McLellan
IPC分类号： G06F9/38 , G06F13/00
CPC分类号： G06F9/3851 , G06F9/384
摘要： A circuit and a scheme for register renaming responsive to a thread ID register, comprises: a plurality of physical registers; a plurality of architectual registers; a rename logic circuit where every write to an architectual register of the plurality of architectural registers is assigned a new physical register of the plurality of physical registers; a register map circuit containing a corresponding entry for each of the plurality of architectual registers. The register map circuit is responsive to the thread ID register such that a different physical map is selected for architectual registers of each thread, whereby the plurality of architectual registers can be greater than the plurality of physical registers.
摘要翻译：响应于线程ID寄存器的用于寄存器重命名的电路和方案包括：多个物理寄存器; 多个架构寄存器; 重命名逻辑电路，其中对所述多个架构寄存器的结构寄存器的每个写入被分配了所述多个物理寄存器的新物理寄存器; 寄存器映射电路，其包含用于所述多个结构寄存器中的每一个的对应条目。寄存器映射电路响应于线程ID寄存器，使得为每个线程的架构寄存器选择不同的物理映射，由此多个架构寄存器可以大于多个物理寄存器。

7. 发明授权

US5727346A Apparatus for quick-releasable attachment of a target illuminating device to a firearm 失效
标题翻译：用于将目标照明装置快速可拆卸地附接到枪支的装置
公开(公告)号：US5727346A
公开(公告)日：1998-03-17
申请号：US784156
申请日：1997-01-15
申请人： Donald Lawrence Lazzarini , Harry Dwyer, III
发明人： Donald Lawrence Lazzarini , Harry Dwyer, III
IPC分类号： F41G1/35 , F41G1/34
CPC分类号： F41G1/35
摘要： A mounting apparatus for the quick-detachable securing of a flashlight or a like target illumination device to a firearm. The mounting device includes a passage for receiving the barrel of the flashlight or the like. The passage is provided with a resilient means to press the flashlight longitudinally along approximately the same axis as the firearm's barrel in opposition to a springably-positioned latch system engaging one end of the flashlight which prevents its dislodgment upon movement of the firearm during handling or discharge, yet enabling relatively quick, one-handed release and replacement of the entire flashlight. The flashlight or the like is prevented from rotating in the passage by a groove in the interior of the passage that engages part of the flashlight body thereby indexing it so that the flashlight's controls are always in the same position and accessible to the user.
摘要翻译：一种用于将手电筒或类似目标照明装置快速可拆卸地固定到枪支的安装装置。安装装置包括用于接收手电筒等的通道。该通道设置有弹性装置，以与手枪的枪管沿着大致相同的轴线纵向按压手电筒，与弹夹定位的闩锁系统相接触，该闩锁系统与手电筒的一端相接触，防止在手枪在操作或放电期间移动时其移动，但能够相对快速，单手释放和更换整个手电筒。防止手电筒等通过通道内部的沟槽旋转，该凹槽与手电筒主体的一部分接合，从而将手电筒的控制总是处于相同的位置并且可由用户访问。

8. 发明授权

US5630157A Computer organization for multiple and out-of-order execution of condition code testing and setting instructions 失效
标题翻译：计算机组织进行条件代码测试和设置指令的多次和无序执行
公开(公告)号：US5630157A
公开(公告)日：1997-05-13
申请号：US328933
申请日：1994-10-25
申请人： Harry Dwyer, III
发明人： Harry Dwyer, III
IPC分类号： F02B75/02 , G06F9/38 , G06F11/34
CPC分类号： G06F9/3885 , G06F9/30072 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3855 , G06F9/3857 , G06F9/3863 , F02B2075/027 , G06F11/3461
摘要： Computer system with multiple, out-of-order, instruction issuing system suitable for superscalar processors with a RISC organization, also has a Fast Dispatch Stack (FDS), a dynamic instruction scheduling system that may issue multiple, out-of-order, instructions each cycle to functional units as dependencies allow. The basic issuing mechanism supports a short cycle time and its capabilities are augmented. Condition code dependent instructions issue in multiples and out-of-order. A fast register renaming scheme is presented. An instruction squashing technique enables fast precise interrupts and branch prediction. Instructions preceding and following one or more predicted conditional branch instructions may issue out-of-order and concurrently. The effects of executed instructions following an incorrectly predicted branch instruction or an instruction that causes a precise interrupt are undone in one machine cycle.
摘要翻译：具有适用于具有RISC组织的超标量处理器的具有多个无序指令发布系统的计算机系统还具有快速调度堆栈（FDS），动态指令调度系统，其可以发出多个无序指令每个循环到功能单元作为依赖允许。基本发布机制支持短周期时间，功能增强。条件代码相关的指令以多次和乱序发出。提出了快速注册重命名方案。指令压缩技术可实现快速精确中断和分支预测。一个或多个预测的条件分支指令之前和之后的指令可以发出乱序和同时发生。在错误预测的分支指令或导致精确中断的指令之后的执行指令的影响在一个机器周期中被撤消。

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