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1. 发明授权

US09870384B2 Database system transaction management 有权
公开(公告)号：US09870384B2
公开(公告)日：2018-01-16
申请号：US13435281
申请日：2012-03-30
申请人： Harold Wade Cain, III , Donna N. Dillenberger , Michel H. T. Hack , Hong Min , Gong Su , James Zu-Chia Teng
发明人： Harold Wade Cain, III , Donna N. Dillenberger , Michel H. T. Hack , Hong Min , Gong Su , James Zu-Chia Teng
IPC分类号： G06F17/30
CPC分类号： G06F17/30351
摘要： Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.

2. 发明申请

US20130262424A1 DATABASE SYSTEM TRANSACTION MANAGEMENT 有权
标题翻译：数据库系统交易管理
公开(公告)号：US20130262424A1
公开(公告)日：2013-10-03
申请号：US13435281
申请日：2012-03-30
申请人： Harold Wade Cain, III , Donna N. Dillenberger , Michel H.T. Hack , Hong Min , Gong Su , James Zu-Chia Teng
发明人： Harold Wade Cain, III , Donna N. Dillenberger , Michel H.T. Hack , Hong Min , Gong Su , James Zu-Chia Teng
IPC分类号： G06F17/30
CPC分类号： G06F17/30351
摘要： Systems, methods, and products for database system transaction management are provided herein. One aspect provides for annotating via a computing device at least one data object residing on the computing device utilizing at least one transaction tag, the at least one transaction tag being configured to indicate a status of an associated data object; processing at least one database transaction utilizing a transactional memory process, wherein access to the at least one data object is determined based on the status of the at least one data object; and updating the status of the at least one data object responsive to an attempted access of the at least one data object by the at least one database transaction. Other embodiments and aspects are also described herein.
摘要翻译：本文提供了数据库系统事务管理的系统，方法和产品。一个方面提供了一种使用至少一个交易标签通过计算设备对位于所述计算设备上的至少一个数据对象的注释，所述至少一个交易标签被配置为指示相关联的数据对象的状态; 使用事务性存储器处理来处理至少一个数据库事务，其中基于所述至少一个数据对象的状态来确定对所述至少一个数据对象的访问; 以及响应于所述至少一个数据库事务对所述至少一个数据对象的尝试访问来更新所述至少一个数据对象的状态。本文还描述了其它实施例和方面。

3. 发明申请

US20130007374A1 Checkpointed Tag Prefetcher 失效
标题翻译：检查点标签预取器
公开(公告)号：US20130007374A1
公开(公告)日：2013-01-03
申请号：US13610071
申请日：2012-09-11
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F12/08
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A dual-mode prefetch system for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags identifying the data stored in the data array; a checkpoint tag array storing data identification information; and a cache controller with prefetch logic.
摘要翻译：用于实现检查点标签预取的双模预取系统包括：用于存储从高速缓冲存储器取出的数据的数据阵列; 一组标识存储在数据阵列中的数据的缓存标签; 存储数据识别信息的检查点标签阵列; 以及具有预取逻辑的缓存控制器。

4. 发明申请

US20080288926A1 Computer Implemented Method and System for Accurate, Efficient and Adaptive Calling Context Profiling 失效
标题翻译：计算机实现方法和系统，用于精确，高效和自适应的调用上下文分析
公开(公告)号：US20080288926A1
公开(公告)日：2008-11-20
申请号：US12141222
申请日：2008-06-18
申请人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
发明人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio Jose Serrano , Xiaotong Zhuang
IPC分类号： G06F9/44
CPC分类号： G06F11/3466 , G06F2201/865
摘要： Computer implemented method, system and computer usable program code for profiling the execution of an application that is both space-and time-efficient and highly accurate. A computer implemented method for profiling the execution of an application includes sampling execution characteristics of the application at a plurality of sampling points to provide samples, and deriving a calling context of the samples. The application is continuously executed between sampling points while additional profiling data is gathered.
摘要翻译：计算机实现的方法，系统和计算机可用程序代码，用于分析空间和时间高效且高度准确的应用程序的执行。用于分析应用的执行的计算机实现的方法包括在多个采样点处对应用的采样执行特性，以提供采样，以及导出样本的呼叫上下文。应用程序在采样点之间持续执行，同时收集附加的分析数据。

5. 发明授权

US08683127B2 Checkpointed tag prefetcher 有权
标题翻译：检查点标签预取器
公开(公告)号：US08683127B2
公开(公告)日：2014-03-25
申请号：US13564829
申请日：2012-08-02
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F13/00 , G06F9/26
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A cache management method using checkpoint tags in checkpoint mode includes steps of: receiving a request to save data; fetching at least one cache block including the data from cache memory; writing the data from the at least one cache block into the data array; writing a physical address and metadata of the cache block into an array of cache memory tags; and upon receipt of a restore request: fetching an identifier for the at least one cache block stored in the checkpoint tag array; reloading the cache memory with the at least one cache block in the checkpoint tag array; and switching to normal mode.
摘要翻译：在检查点模式中使用检查点标签的高速缓存管理方法包括以下步骤：接收保存数据的请求; 从高速缓冲存储器中取出包含数据的至少一个缓存块; 将来自所述至少一个高速缓存块的数据写入所述数据阵列; 将高速缓存块的物理地址和元数据写入高速缓存存储器标签阵列; 并且在接收到恢复请求时：获取存储在所述检查点标签阵列中的所述至少一个高速缓存块的标识符; 使用所述检查点标签阵列中的所述至少一个高速缓存块重新加载所述高速缓冲存储器; 并切换到正常模式。

6. 发明授权

US08341352B2 Checkpointed tag prefetcher 有权
标题翻译：检查点标签预取器
公开(公告)号：US08341352B2
公开(公告)日：2012-12-25
申请号：US11736548
申请日：2007-04-17
申请人： Harold Wade Cain, III , Jong-Deok Choi
发明人： Harold Wade Cain, III , Jong-Deok Choi
IPC分类号： G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6024
摘要： A dual-mode prefetch mechanism for implementing checkpoint tag prefetching includes: a data array for storing data fetched from cache memory; a set of cache tags for identifying the data stored in the data array; a set of checkpoint tags for storing data identification; a cache controller including prefetch logic, the prefetch logic including a checkpoint prefetch controller and a checkpoint prefetch operator.
摘要翻译：用于实现检查点标签预取的双模式预取机制包括：用于存储从高速缓冲存储器取出的数据的数据阵列; 用于识别存储在数据阵列中的数据的一组缓存标签; 一组用于存储数据识别的检查点标签; 包括预取逻辑的高速缓存控制器，预取逻辑包括检查点预取控制器和检查点预取操作符。

7. 发明申请

US20100138571A1 METHOD AND SYSTEM FOR A SHARING BUFFER 有权
标题翻译：共享缓冲器的方法和系统
公开(公告)号：US20100138571A1
公开(公告)日：2010-06-03
申请号：US12623496
申请日：2009-11-23
申请人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
发明人： Harold Wade Cain, III , Rui Hou , Xiaowei Shen , Huayong Wang
IPC分类号： G06F5/14 , G06F9/46
CPC分类号： G06F9/30087 , G06F9/467 , G06F9/5016
摘要： A system, method, and computer readable article of manufacture for sharing buffer management. The system includes: a predictor module to predict at runtime a transaction data size of a transaction according to history information of the transaction; and a resource management module to allocate sharing buffer resources for the transaction according to the predicted transaction data size in response to beginning of the transaction, to record an actual sharing buffer size occupied by the transaction in response to the successful commitment of the transaction, and to update the history information of the transaction.
摘要翻译：用于共享缓冲区管理的系统，方法和计算机可读制造品。该系统包括：预测器模块，用于根据交易的历史信息在运行时预测交易的交易数据大小; 以及资源管理模块，用于响应于所述事务的开始，根据预测的事务数据大小来分配所述事务的共享缓冲器资源，以响应所述事务的成功承诺来记录所述事务所占用的实际共享缓冲区大小;以及更新交易的历史信息。

8. 发明申请

US20090113132A1 PREFERRED WRITE-MOSTLY DATA CACHE REPLACEMENT POLICIES 失效
标题翻译：优先写入的数据高速缓存替代政策
公开(公告)号：US20090113132A1
公开(公告)日：2009-04-30
申请号：US11923625
申请日：2007-10-24
申请人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio J. Serrano
发明人： Harold Wade Cain, III , Jong-Deok Choi , Mauricio J. Serrano
IPC分类号： G06F13/28
CPC分类号： G06F12/127 , G06F2212/1021
摘要： A computer-implemented method of cache replacement includes steps of: determining whether each cache block in a cache memory is a read or a write block; augmenting metadata associated with each cache block with an indicator of the type of access; receiving an access request resulting in a cache miss, the cache miss indicating that a cache block will need to be replaced; examining the indicator in the metadata of each cache block for determining a probability that said cache block will be replaced; and selecting for replacement the cache block with the highest probability of replacement.
摘要翻译：计算机实现的高速缓存替换方法包括以下步骤：确定高速缓冲存储器中的每个高速缓存块是读还是写块; 使用所述访问类型的指示符来增强与每个高速缓存块相关联的元数据; 接收导致高速缓存未命中的访问请求，指示高速缓存块将需要被替换的高速缓存未命中; 检查每个高速缓存块的元数据中的指示符，以确定所述高速缓存块将被替换的概率; 并以最高的替换概率选择替换高速缓存块。

9. 发明申请

US20130159678A1 Code optimization by memory barrier removal and enclosure within transaction 有权
标题翻译：通过内存障碍去除和事务中的机箱进行代码优化
公开(公告)号：US20130159678A1
公开(公告)日：2013-06-20
申请号：US13326320
申请日：2011-12-15
申请人： Toshihiko Koju , Takuya Nakaike , Ali Ijaz Sheikh , Harold Wade Cain, III , Maged M. Michael
发明人： Toshihiko Koju , Takuya Nakaike , Ali Ijaz Sheikh , Harold Wade Cain, III , Maged M. Michael
IPC分类号： G06F9/30
CPC分类号： G06F9/522 , G06F8/4441 , G06F8/458 , G06F9/3004 , G06F9/30043 , G06F9/30087 , G06F9/3851 , G06F9/466 , G06F9/467 , G06F11/3409 , G06F11/3466 , G06F2201/81 , G06F2201/865 , G06F2201/88
摘要： A code section of a computer program to be executed by a computing device includes memory barrier instructions. Where the code section satisfies a threshold, the code section is modified, by enclosing the code section within a transaction that employs hardware transactional memory of the computing device, and removing the memory barrier instructions from the code section. Execution of the code section as has been enclosed within the transaction can be monitored to yield monitoring results. Where the monitoring results satisfy an abort threshold corresponding to excessive aborting of the execution of the code section as has been enclosed within the transaction, the code section is split into code sub-sections, and each code sub-section enclosed within a separate transaction that employs the hardware transactional memory. Splitting the code section sections and enclosing each code sub-section within a separate transaction can decrease occurrence of the code section aborting during execution.
摘要翻译：由计算设备执行的计算机程序的代码部分包括存储器障碍指令。在代码部分满足阈值的情况下，通过将代码部分包围在使用计算设备的硬件事务存储器的事务中，并从代码部分移除存储器障碍指令来修改代码部分。可以监视执行代码部分的内容，以便产生监视结果。如果监视结果满足对应于已经包含在交易内的代码段的执行的过度中止对应的中止阈值，则代码部分被分割成代码子部分，并且每个代码子部分包含在单独的交易中，采用硬件事务内存。拆分代码段部分并在单独的事务中包围每个代码子部分可以减少代码段在执行期间中止的发生。

10. 发明授权

US08392694B2 System and method for software initiated checkpoint operations 有权
标题翻译：用于软件启动的检查点操作的系统和方法
公开(公告)号：US08392694B2
公开(公告)日：2013-03-05
申请号：US12559643
申请日：2009-09-15
申请人： Colin B. Blundell , Harold Wade Cain, III , Gheorghe C. Cascaval , Maged Milad Michael
发明人： Colin B. Blundell , Harold Wade Cain, III , Gheorghe C. Cascaval , Maged Milad Michael
IPC分类号： G06F7/38 , G06F9/00 , G06F9/44 , G06F15/00
CPC分类号： G06F9/30076 , G06F11/1407
摘要： A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints.
摘要翻译：一种方法，系统和计算机程序产品，用于发出用于创建寄存器文件和存储器的检查点的一个或多个软件发起的操作，以及用于将寄存器文件和存储器恢复到检查点状态。在执行检查点操作时，系统返回指示成功或失败的条件代码。当条件代码设置为等于1时，将启动一个或多个检查点。每次启动一个或多个检查点时，都会存储寄存器文件和门控存储缓冲区的内容。当检查点创建时，系统在达到硬件检查点容量时通知软件。利用一个或多个软件检查点，硬件检查点和处理程序检查点来提供更精确的恢复点。在软件执行期间，寄存器文件和门控存储缓冲区可以由一个或多个以前的检查点定义来恢复。

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