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1. 发明申请

US20130012254A1 ADJUSTING A SIGNAL-TO-INTERFERENCE RATIO TARGET BASED ON A SIGNAL CHARACTERISTIC 有权
标题翻译：基于信号特征调整信号干扰比目标
公开(公告)号：US20130012254A1
公开(公告)日：2013-01-10
申请号：US13347057
申请日：2012-01-10
申请人： Harish Venkatachari , An-swol C. Hu , Rajiv R. Nambiar , Venkata Chalapathi Rao S. Emani , Ravi Gopalan , Sunny Arora
发明人： Harish Venkatachari , An-swol C. Hu , Rajiv R. Nambiar , Venkata Chalapathi Rao S. Emani , Ravi Gopalan , Sunny Arora
IPC分类号： H04W52/24
CPC分类号： H04W52/241 , H04W52/12 , H04W52/146 , H04W72/0473
摘要： A particular method includes transmitting a message corresponding to a reporting event detected at a mobile device, where the reporting event is associated with a network condition that decreases a likelihood of the mobile device successfully decoding a reply to the message. The method also includes, in response to transmitting the message, increasing a signal-to-interference ratio (SIR) target of the mobile device.
摘要翻译：一种特定方法包括发送对应于在移动设备处检测到的报告事件的消息，其中报告事件与降低移动设备成功解码对消息的回复的可能性的网络条件相关联。该方法还包括响应于发送消息，增加移动设备的信号干扰比（SIR）目标。

2. 发明授权

US08965444B2 Adjusting a signal-to-interference ratio target based on a signal characteristic 有权
标题翻译：基于信号特性调整信号干扰比目标
公开(公告)号：US08965444B2
公开(公告)日：2015-02-24
申请号：US13347057
申请日：2012-01-10
申请人： Harish Venkatachari , An-swol C. Hu , Rajiv R. Nambiar , Venkata Chalapathi Rao S. Emani , Ravi Gopalan , Sunny Arora
发明人： Harish Venkatachari , An-swol C. Hu , Rajiv R. Nambiar , Venkata Chalapathi Rao S. Emani , Ravi Gopalan , Sunny Arora
IPC分类号： H04W52/24 , H04W52/12 , H04W52/14 , H04W72/04
CPC分类号： H04W52/241 , H04W52/12 , H04W52/146 , H04W72/0473
摘要： A particular method includes transmitting a message corresponding to a reporting event detected at a mobile device, where the reporting event is associated with a network condition that decreases a likelihood of the mobile device successfully decoding a reply to the message. The method also includes, in response to transmitting the message, increasing a signal-to-interference ratio (SIR) target of the mobile device.
摘要翻译：一种特定方法包括发送对应于在移动设备处检测到的报告事件的消息，其中报告事件与降低移动设备成功解码对消息的回复的可能性的网络条件相关联。该方法还包括响应于发送消息，增加移动设备的信号干扰比（SIR）目标。

3. 发明授权

US08464117B2 System for testing integrated circuit with asynchronous clock domains 有权
标题翻译：具有异步时钟域的集成电路测试系统
公开(公告)号：US08464117B2
公开(公告)日：2013-06-11
申请号：US12786467
申请日：2010-05-25
申请人： Shruti Rakheja , Sunny Arora , Pawan Deep Gandhi , Rashmi Moudgil
发明人： Shruti Rakheja , Sunny Arora , Pawan Deep Gandhi , Rashmi Moudgil
IPC分类号： G01R31/28
CPC分类号： G01R31/318594 , G01R31/318558
摘要： A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.
摘要翻译：用于扫描测试集成电路的各个时钟域的系统包括时钟门控制单元和时钟门控单元。时钟门控单元接收从外部通过集成电路的一个封装引脚提供的单个测试时钟信号。时钟门控制单元向时钟门控单元提供时钟门控制信号。时钟门控单元基于时钟门控制信号产生时间交错的时钟信号。

4. 发明授权

US07834657B1 Inverter circuit with compensation for threshold voltage variations 有权
标题翻译：逆变电路补偿阈值电压变化
公开(公告)号：US07834657B1
公开(公告)日：2010-11-16
申请号：US12685680
申请日：2010-01-12
申请人： Sunny Arora , Mukesh Bansal , Dipesh K. Gupta , Ankesh Jain , Gaurav Jain , Ritika Singh
发明人： Sunny Arora , Mukesh Bansal , Dipesh K. Gupta , Ankesh Jain , Gaurav Jain , Ritika Singh
IPC分类号： H03K17/16 , H03K19/003
CPC分类号： H03K19/00384 , H03K17/302 , H03K2217/0018
摘要： An inverter circuit has a digital signal amplitude converter having an input coupled to an inverter circuit input node, and an amplitude converter output. A positive threshold voltage compensation generator has a positive threshold voltage compensation generator input coupled to the amplitude converter output. A negative threshold voltage compensation generator has a negative threshold voltage compensation generator input coupled to the inverter circuit input node, and a negative threshold voltage compensation generator output. A multiplexer has a first input coupled to the positive threshold voltage compensation generator output, a second input, coupled to the negative threshold voltage compensation generator output, and a multiplexer output. An inverter module has an output providing an inverter circuit output node, and an inverter module input is coupled to the multiplexer output. The inverter circuit at least partially compensates for variations in a threshold voltage associated with switching of transistors that form the inverter module.
摘要翻译：逆变器电路具有数字信号幅度转换器，其具有耦合到反相器电路输入节点的输入端和幅度转换器输出端。正阈值电压补偿发生器具有耦合到幅度转换器输出的正阈值电压补偿发生器输入。负阈值电压补偿发生器具有耦合到逆变器电路输入节点的负阈值电压补偿发生器输入和负阈值电压补偿发生器输出。复用器具有耦合到正阈值电压补偿发生器输出的第一输入，耦合到负阈值电压补偿发生器输出的第二输入和多路复用器输出。逆变器模块具有提供逆变器电路输出节点的输出，并且反相器模块输入耦合到多路复用器输出。逆变器电路至少部分地补偿与形成逆变器模块的晶体管的切换相关的阈值电压的变化。

5. 发明授权

US08120404B2 Flip-flop circuit with internal level shifter 有权
标题翻译：具有内部电平转换器的触发器电路
公开(公告)号：US08120404B2
公开(公告)日：2012-02-21
申请号：US13097054
申请日：2011-04-29
申请人： Sunny Arora , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
发明人： Sunny Arora , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
IPC分类号： H03K3/289
CPC分类号： H03K3/356052 , H03K3/356121 , H03K3/356147
摘要： A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.
摘要翻译：具有内部电平移位器的触发器电路包括输入级，时钟输入级，输出级和电平转换级。输出级基于由输入级接收的输入信号和由时钟输入级接收的时钟信号产生输出信号。电平移位级使输出信号的电压电平上升。

6. 发明申请

US20110296265A1 SYSTEM FOR TESTING INTEGRATED CIRCUIT WITH ASYNCHRONOUS CLOCK DOMAINS 有权
标题翻译：用异步时钟域测试集成电路的系统
公开(公告)号：US20110296265A1
公开(公告)日：2011-12-01
申请号：US12786467
申请日：2010-05-25
申请人： Shruti RAKHEJA , Sunny Arora , Pawan Deep Gandhi , Rashmi Moudgil
发明人： Shruti RAKHEJA , Sunny Arora , Pawan Deep Gandhi , Rashmi Moudgil
IPC分类号： G01R31/3177 , G06F11/25
CPC分类号： G01R31/318594 , G01R31/318558
摘要： A system for scan testing various clock domains of an integrated circuit includes a clock gate control unit and clock gating cells. The clock gating cells receive a single test clock signal provided externally through one package pin of the integrated circuit. The clock gate control unit provides clock gate control signals to the clock gating cells. The clock gating cells generate time-staggered clock signals based on the clock gate control signals.
摘要翻译：用于扫描测试集成电路的各个时钟域的系统包括时钟门控制单元和时钟门控单元。时钟门控单元接收从外部通过集成电路的一个封装引脚提供的单个测试时钟信号。时钟门控制单元向时钟门控单元提供时钟门控制信号。时钟门控单元基于时钟门控制信号产生时间交错的时钟信号。

7. 发明授权

US07956662B2 Flip-flop circuit with internal level shifter 有权
标题翻译：具有内部电平转换器的触发器电路
公开(公告)号：US07956662B2
公开(公告)日：2011-06-07
申请号：US12624360
申请日：2009-11-23
申请人： Sunny Arora , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
发明人： Sunny Arora , Kumar Abhishek , Mukesh Bansal , Shilpa Gupta
IPC分类号： H03K3/356
CPC分类号： H03K3/356052 , H03K3/356121 , H03K3/356147
摘要： A flip-flop circuit with an internal level shifter includes an input stage, a clock input stage, an output stage and a level shifting stage. The output stage generates an output signal based on an input signal received by the input stage and a clock signal received by the clock input stage. The level shifting stage shifts-up the voltage level of the output signal.
摘要翻译：具有内部电平移位器的触发器电路包括输入级，时钟输入级，输出级和电平转换级。输出级基于由输入级接收的输入信号和由时钟输入级接收的时钟信号产生输出信号。电平移位级使输出信号的电压电平上升。

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