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    • 5. 发明授权
    • On-chip radial cavity power divider/combiner
    • 片上径向腔功率分配器/组合器
    • US08643191B2
    • 2014-02-04
    • US13358792
    • 2012-01-26
    • Hanyi DingPinping SunGuoan WangWayne H. Woods, Jr.
    • Hanyi DingPinping SunGuoan WangWayne H. Woods, Jr.
    • H01L23/48H01L23/52H01L29/40
    • H01L23/481H01L23/66H01L2224/16225H01L2924/1305H01L2924/15311H01L2924/00
    • Disclosed is a chip with a power divider/combiner, a module incorporating the chip and associated methods. The divider/combiner comprises first and second metal layers on opposite sides of a substrate. Interconnects extend through the substrate and comprise: a first interconnect, second interconnects annularly arranged about the first interconnect and third interconnects annularly arranged about the second interconnects. Each interconnect comprises one or more through silicon vias lined/filled with a conductor. For a power divider, an opening in the first metal layer at the first interconnect comprises an input port for receiving power and openings in the first or second metal layer at the second interconnects comprise output ports for applying power to other devices. For a power combiner, openings in the first or second metal layer at the second interconnects comprise the input ports and an opening in the first metal layer at the first interconnect comprises an output port.
    • 公开了具有功率分配器/组合器的芯片,包括芯片的模块和相关联的方法。 分隔器/组合器包括在衬底的相对侧上的第一和第二金属层。 互连件延伸穿过衬底并且包括:第一互连,围绕第一互连环形布置的第二互连和围绕第二互连环形布置的第三互连。 每个互连包括一个或多个内衬/填充有导体的通孔硅通孔。 对于功率分配器,第一互连处的第一金属层中的开口包括用于接收功率的输入端口,并且在第二互连处的第一或第二金属层中的开口包括用于向其它器件施加电力的输出端口。 对于功率组合器,在第二互连处的第一或第二金属层中的开口包括输入端口,并且在第一互连处的第一金属层中的开口包括输出端口。
    • 10. 发明授权
    • On-chip variable delay transmission line with fixed characteristic impedance
    • 具有固定特性阻抗的片上可变延迟传输线
    • US08508314B2
    • 2013-08-13
    • US13441245
    • 2012-04-06
    • Hanyi DingWayne H. Woods, Jr.
    • Hanyi DingWayne H. Woods, Jr.
    • H01P1/18
    • H01P9/00H01P1/184
    • A design structure, structure, and method for providing an on-chip variable delay transmission line with a fixed characteristic impedance. A method of manufacturing a transmission line structure includes forming a signal line of the transmission line structure, forming a first ground return structure that causes a first delay and a first characteristic impedance in the transmission line structure, and forming a second ground return structure that causes a second delay and a second characteristic impedance in the transmission line structure. The first delay is different from the second delay, and the first characteristic impedance is substantially the same as the second characteristic impedance.
    • 一种用于提供具有固定特性阻抗的片上可变延迟传输线的设计结构,结构和方法。 制造传输线结构的方法包括形成传输线结构的信号线,形成在传输线结构中引起第一延迟和第一特性阻抗的第一接地返回结构,以及形成第二接地返回结构,其导致 传输线结构中的第二延迟和第二特性阻抗。 第一延迟与第二延迟不同,第一特征阻抗基本上与第二特征阻抗相同。