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    • 9. 发明申请
    • Manufacturing method for an integrated semiconductor contact structure having an improved aluminum fill
    • 具有改进的铝填充的集成半导体接触结构的制造方法
    • US20070243708A1
    • 2007-10-18
    • US11402675
    • 2006-04-12
    • Jens HahnTom RichterDetlef WeberChung-Hsin Lin
    • Jens HahnTom RichterDetlef WeberChung-Hsin Lin
    • H01L21/4763H01L21/44
    • C23C14/046H01L21/2855H01L21/76882
    • The present invention provides a manufacturing method for an integrated semiconductor contact structure having an improved Aluminum fill comprising the steps of: forming contact holes in an insulation layer provided on a wafer, said contact holes having a respective bottom and respective sidewalls, said bottoms including a respective conductive area; introducing said wafer into a first PVD deposition chamber, said first PVD deposition chamber including a wafer bias means; and cold depositing a first Aluminum layer on the wafer in said first PVD deposition chamber, said first Aluminum layer covering said bottoms and said sidewalls of said contact holes and forming a seed layer; wherein during said step of cold depositing said first Aluminum layer on the wafer in said first PVD deposition chamber said wafer bias means is set to a bias in the range between 20 W and 700 W or −50 V to −800 V.
    • 本发明提供一种具有改进的铝填充物的集成半导体接触结构的制造方法,包括以下步骤:在设置在晶片上的绝缘层中形成接触孔,所述接触孔具有相应的底部和相应的侧壁,所述底部包括 各导电面积; 将所述晶片引入第一PVD沉积室,所述第一PVD沉积室包括晶片偏置装置; 并且在所述第一PVD沉积室中在所述晶片上冷沉积第一铝层,所述第一铝层覆盖所述底部和所述接触孔的所述侧壁并形成种子层; 其中在所述第一PVD沉积室中将所述第一铝层冷沉积在所述晶片上的步骤期间,所述晶片偏置装置被设置为在20W和700W之间或-50V至-800V的范围内的偏压。
    • 10. 发明申请
    • Method of fabricating an integrated memory device
    • 制造集成存储器件的方法
    • US20070218629A1
    • 2007-09-20
    • US11375590
    • 2006-03-15
    • Matthias KronkeDetlef Weber
    • Matthias KronkeDetlef Weber
    • H01L21/336
    • H01L27/10858H01L27/10897
    • Method of fabricating an integrated memory device including the steps of providing a semiconductor substrate, including an array region and a support region; providing GC-lines in said array region and in said support region, wherein the GC-lines in said support region have a first height; providing in the array region bit line contacts projecting above said GC-lines, wherein said bit line contacts have a second height being higher than said first height; providing a first isolation layer, the maximum height of said GC-lines in said support region including the coverage of said first isolation layer being lower than said second height; providing a second isolation layer on said first isolation layer; and polishing said first isolation layer and said second isolation layer, such that a planar surface of the integrated memory device is provided and such that said bit line contacts are exposed.
    • 一种集成存储器件的制造方法,包括以下步骤:提供包括阵列区域和支撑区域的半导体衬底; 在所述阵列区域和所述支撑区域中提供GC线,其中所述支撑区域中的GC线具有第一高度; 提供在所述GC线上方突出的阵列区位线触点,其中所述位线触点具有高于所述第一高度的第二高度; 提供第一隔离层,所述支撑区域中所述GC线的最大高度包括所述第一隔离层的覆盖范围低于所述第二高度; 在所述第一隔离层上提供第二隔离层; 并且抛光所述第一隔离层和所述第二隔离层,使得提供所述集成存储器件的平坦表面,并使所述位线触点露出。