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1. 发明授权

US08330274B2 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08330274B2
公开(公告)日：2012-12-11
申请号：US12893009
申请日：2010-09-29
申请人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
发明人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
IPC分类号： H01L23/48
CPC分类号： H01L21/76843 , H01L21/76807 , H01L21/76879 , H01L23/49816 , H01L23/53223 , H01L23/53238 , H01L23/53252 , H01L23/53266 , H01L24/03 , H01L24/10 , H01L24/13 , H01L2224/0401 , H01L2224/13 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01023 , H01L2924/01027 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01037 , H01L2924/01042 , H01L2924/01044 , H01L2924/01047 , H01L2924/0105 , H01L2924/0106 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/10329 , H01L2924/12042 , H01L2924/14 , H01L2924/15788 , H01L2924/00
摘要： One or more embodiments relate to a method of forming a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a seed layer over the barrier layer; forming an inhibitor layer over the seed layer; removing a portion of said inhibitor layer to expose a portion of the seed layer; and selectively depositing a fill layer on the exposed seed layer.
摘要翻译：一个或多个实施例涉及一种形成半导体结构的方法，包括：提供工件; 在工件上形成阻挡层; 在阻挡层上形成种子层; 在种子层上形成抑制层; 去除所述抑制剂层的一部分以暴露所述种子层的一部分; 并且在曝光的种子层上选择性地沉积填充层。

2. 发明授权

US08148257B1 Semiconductor structure and method for making same 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US08148257B1
公开(公告)日：2012-04-03
申请号：US12894190
申请日：2010-09-30
申请人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
发明人： Hans-Joachim Barth , Gottfried Beer , Joern Plagmann , Jens Pohl , Werner Robl , Rainer Steiner , Mathias Vaupel
IPC分类号： H01L21/44 , H01L21/4763 , H01L21/469
CPC分类号： H01L23/53238 , H01L21/76846 , H01L21/76865 , H01L21/76873 , H01L21/76879 , H01L21/76885 , H01L23/53223 , H01L23/53252 , H01L23/53266 , H01L2924/0002 , H01L2924/00
摘要： One or more embodiments relate to a method of forming an electronic device, comprising: providing a workpiece; forming a first barrier layer over the workpiece; forming an intermediate conductive layer over the first barrier layer; forming a second barrier layer over the intermediate conductive layer; forming a seed layer over the second barrier layer; removing a portion of the seed layer to leave a remaining portion of the seed layer and to expose a portion of the second barrier layer; and electroplating a fill layer on the remaining portion of the seed layer.
摘要翻译：一个或多个实施例涉及一种形成电子设备的方法，包括：提供工件; 在工件上形成第一阻挡层; 在所述第一阻挡层上形成中间导电层; 在所述中间导电层上形成第二阻挡层; 在所述第二阻挡层上形成种子层; 去除种子层的一部分以留下种子层的剩余部分并暴露第二阻挡层的一部分; 并在种子层的剩余部分上电镀填充层。

3. 发明授权

US08334202B2 Device fabricated using an electroplating process 有权
标题翻译：使用电镀工艺制造的器件
公开(公告)号：US08334202B2
公开(公告)日：2012-12-18
申请号：US12611609
申请日：2009-11-03
申请人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
发明人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
IPC分类号： H01L23/48
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/76873 , H01L21/76879 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/82 , H01L24/97 , H01L2221/1089 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要翻译：一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。该方法包括在电介质层上施加第一种子层，在种子层上施加惰性层，以及构造惰性层，第一种子层和电介质层以暴露至少一部分接触。该方法包括在结构化介电层和触点的暴露部分上施加第二种子层，使得第二籽晶层与结构化的第一籽晶层电接触。该方法包括在第二种子层上电镀金属。

4. 发明申请

US20110101532A1 DEVICE FABRICATED USING AN ELECTROPLATING PROCESS 有权
标题翻译：使用电镀工艺制作的器件
公开(公告)号：US20110101532A1
公开(公告)日：2011-05-05
申请号：US12611609
申请日：2009-11-03
申请人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
发明人： Jens Pohl , Hans-Joachim Barth , Gottfried Beer , Rainer Steiner , Werner Robl , Mathias Vaupel
IPC分类号： H01L23/48 , H05K1/00 , C25D5/00 , C25D5/34
CPC分类号： H01L23/5389 , H01L21/486 , H01L21/76873 , H01L21/76879 , H01L23/49816 , H01L23/49822 , H01L23/49827 , H01L24/82 , H01L24/97 , H01L2221/1089 , H01L2224/97 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01028 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/1461 , H01L2924/181 , H01L2224/82 , H01L2924/00
摘要： A method for fabricating a device includes providing a substrate including at least one contact and applying a dielectric layer over the substrate. The method includes applying a first seed layer over the dielectric layer, applying an inert layer over the seed layer, and structuring the inert layer, the first seed layer, and the dielectric layer to expose at least a portion of the contact. The method includes applying a second seed layer over exposed portions of the structured dielectric layer and the contact such that the second seed layer makes electrical contact with the structured first seed layer. The method includes electroplating a metal on the second seed layer.
摘要翻译：一种用于制造器件的方法包括提供包括至少一个接触的衬底并在衬底上施加电介质层。该方法包括在电介质层上施加第一种子层，在种子层上施加惰性层，以及构造惰性层，第一籽晶层和电介质层以暴露至少一部分接触。该方法包括在结构化介电层和触点的暴露部分上施加第二种子层，使得第二籽晶层与结构化的第一籽晶层电接触。该方法包括在第二种子层上电镀金属。

5. 发明授权

US08072071B2 Semiconductor device including conductive element 有权
标题翻译：包括导电元件的半导体器件
公开(公告)号：US08072071B2
公开(公告)日：2011-12-06
申请号：US12389103
申请日：2009-02-19
申请人： Rainer Steiner , Jens Pohl , Werner Robl , Markus Brunnbauer , Gottfried Beer
发明人： Rainer Steiner , Jens Pohl , Werner Robl , Markus Brunnbauer , Gottfried Beer
IPC分类号： H01L23/498
CPC分类号： H01L23/528 , H01L21/561 , H01L21/568 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/20 , H01L2224/02351 , H01L2224/03462 , H01L2224/0361 , H01L2224/03622 , H01L2224/0401 , H01L2224/04105 , H01L2224/05006 , H01L2224/05012 , H01L2224/05017 , H01L2224/05546 , H01L2224/05548 , H01L2224/05553 , H01L2224/05555 , H01L2224/05557 , H01L2224/05559 , H01L2224/05567 , H01L2224/05568 , H01L2224/05647 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/97 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2224/83 , H01L2924/00014 , H01L2924/01014 , H01L2924/00
摘要： A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.
摘要翻译：半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。导电元件包括嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分垂直于第一部分和第二部分。

6. 发明申请

US20110291256A1 Method for Fabricating a Semiconductor Chip Package and Semiconductor Chip Package 审中-公开
标题翻译：制造半导体芯片封装和半导体芯片封装的方法
公开(公告)号：US20110291256A1
公开(公告)日：2011-12-01
申请号：US12791443
申请日：2010-06-01
申请人： Rainer Steiner , Jens Pohl , Werner Robl , Gottfried Beer
发明人： Rainer Steiner , Jens Pohl , Werner Robl , Gottfried Beer
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L24/03 , H01L23/3114 , H01L24/05 , H01L24/96 , H01L2224/0332 , H01L2224/0345 , H01L2224/0346 , H01L2224/04105 , H01L2224/05001 , H01L2224/05082 , H01L2224/05546 , H01L2224/05548 , H01L2224/05624 , H01L2224/05644 , H01L2224/05647 , H01L2924/01013 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01059 , H01L2924/01068 , H01L2924/01075 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/18162 , H01L2924/00014 , H01L2924/00
摘要： A semiconductor chip includes a contact pad on a main surface of the chip. An electrically conductive layer is applied onto the contact pad. The main surface of the semiconductor chip is covered with an insulating layer. An electrically conductive contact area is formed within the insulating layer such that the contact area and the insulating layer include coplanar exposed surfaces and the contact area is electrically connected with the electrically conductive layer and includes an extension which is greater than the extension of the electrically conductive layer along a direction parallel to the main surface of the semiconductor chip.
摘要翻译：半导体芯片包括在芯片的主表面上的接触焊盘。将导电层施加到接触垫上。半导体芯片的主表面被绝缘层覆盖。导电接触区域形成在绝缘层内，使得接触区域和绝缘层包括共面的暴露表面，并且接触区域与导电层电连接，并且包括延伸部，其延伸大于导电层沿着与半导体芯片的主表面平行的方向。

7. 发明申请

US20100207272A1 SEMICONDUCTOR DEVICE INCLUDING CONDUCTIVE ELEMENT 有权
标题翻译：包括导电元件的半导体器件
公开(公告)号：US20100207272A1
公开(公告)日：2010-08-19
申请号：US12389103
申请日：2009-02-19
申请人： Rainer Steiner , Jens Pohl , Werner Robl , Markus Brunnbauer , Gottfried Beer
发明人： Rainer Steiner , Jens Pohl , Werner Robl , Markus Brunnbauer , Gottfried Beer
IPC分类号： H01L23/498 , H01L21/768
CPC分类号： H01L23/528 , H01L21/561 , H01L21/568 , H01L23/5283 , H01L24/03 , H01L24/05 , H01L24/13 , H01L24/19 , H01L24/20 , H01L2224/02351 , H01L2224/03462 , H01L2224/0361 , H01L2224/03622 , H01L2224/0401 , H01L2224/04105 , H01L2224/05006 , H01L2224/05012 , H01L2224/05017 , H01L2224/05546 , H01L2224/05548 , H01L2224/05553 , H01L2224/05555 , H01L2224/05557 , H01L2224/05559 , H01L2224/05567 , H01L2224/05568 , H01L2224/05647 , H01L2224/12105 , H01L2224/13023 , H01L2224/131 , H01L2224/97 , H01L2924/01005 , H01L2924/01029 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/10253 , H01L2924/1461 , H01L2224/83 , H01L2924/00014 , H01L2924/01014 , H01L2924/00
摘要： A semiconductor device includes a chip comprising a contact element, a structured dielectric layer over the chip, and a conductive element coupled to the contact element. The conductive element comprises a first portion embedded in the structured dielectric layer, a second portion at least partially spaced apart from the first portion and embedded in the structured dielectric layer, and a third portion contacting a top of the structured dielectric layer and extending at least vertically over the first portion and the second portion.
摘要翻译：半导体器件包括芯片，其包括接触元件，芯片上方的结构化介电层以及耦合到接触元件的导电元件。导电元件包括嵌入结构化电介质层中的第一部分，与第一部分至少部分间隔开并嵌入结构化介电层的第二部分，以及接触结构化介电层顶部并至少延伸的第三部分垂直于第一部分和第二部分。

8. 发明申请

US20060001162A1 Nitride and polysilicon interface with titanium layer 审中-公开
标题翻译：氮化物和多晶硅界面与钛层
公开(公告)号：US20060001162A1
公开(公告)日：2006-01-05
申请号：US11084724
申请日：2005-03-18
申请人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
发明人： Ronald Schutz , Werner Robl , Rajeev Malik , Lawrence Clevenger , Oleg Gluschenkov , Cyril Cabral , Roy Iggulden , Yun-Yu Wang , Keith Wong , Irene McStay
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/7685 , H01L21/28052 , H01L21/28061 , H01L21/76838 , H01L21/76855 , H01L21/823828 , H01L21/823842 , H01L29/4941 , H01L29/51 , H01L29/517 , H01L29/518 , H01L29/78 , H01L2221/1078
摘要： A conductive structure in an integrated circuit (12), and a method of forming the structure, is provided that includes a polysilicon layer (30), a thin layer containing titanium over the polysilicon, a tungsten nitride layer (34) over the titanium-containing layer and a tungsten layer over the tungsten nitride layer. The structure also includes a silicon nitride interfacial region (38) between the polysilicon layer and the titanium-containing layer. The structure withstands high-temperature processing without substantial formation of metal silicides in the polysilicon layer (30) and the tungsten layer (32), and provides low interface resistance between the tungsten layer and the polysilicon layer.
摘要翻译：提供集成电路（12）中的导电结构和形成该结构的方法，其包括多晶硅层（30），在多晶硅上含有钛的薄层，在钛 - 钛层上的氮化钨层（34）并且在氮化钨层上形成钨层。该结构还包括在多晶硅层和含钛层之间的氮化硅界面区域（38）。该结构经受高温处理，而在多晶硅层（30）和钨层（32）中基本不形成金属硅化物，并且在钨层和多晶硅层之间提供低的界面电阻。

9. 发明授权

US06794282B2 Three layer aluminum deposition process for high aspect ratio CL contacts 失效
标题翻译：三层铝沉积工艺，用于高纵横比CL接触
公开(公告)号：US06794282B2
公开(公告)日：2004-09-21
申请号：US10305063
申请日：2002-11-27
申请人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
发明人： Thomas Goebel , Werner Robl , Rajeev Malik , Mihel Seitz
IPC分类号： H01L2144
CPC分类号： H01L27/10888 , H01L21/76882
摘要： A method of forming a semiconductor device includes providing a semiconductor device including a conductor formed thereon. A dielectric layer is formed over the conductor and a recess is formed in the dielectric layer by removing a portion of the dielectric layer to expose at least a portion of the conductor. A first layer of aluminum is deposited over the top surface of the dielectric, along the sidewalls of the dielectric layer and over the exposed portion of the conductor without altering the temperature of the semiconductor device. A second layer of aluminum is deposited over the first layer of aluminum at a temperature greater than about 300° C. A third layer of aluminum is deposited over the second layer of aluminum so as to completely fill the recess in the dielectric layer. The third layer of aluminum is slow deposited at a temperature greater than about 300° C.
摘要翻译：形成半导体器件的方法包括提供包括形成在其上的导体的半导体器件。在导体上形成电介质层，并且通过去除电介质层的一部分以露出导体的至少一部分，在电介质层中形成凹陷。沿着电介质层的侧壁并在导体的暴露部分之上沉积在电介质的顶表面上的第一层铝，而不改变半导体器件的温度。在大于约300℃的温度下，在第一层铝上沉积第二层铝。第三层铝沉积在第二层铝上，以便完全填充介电层中的凹槽。第三层铝在大于约300℃的温度下缓慢沉积

10. 发明授权

US06720212B2 Method of eliminating back-end rerouting in ball grid array packaging 有权
标题翻译：消除球栅阵列封装中后端重路由的方法
公开(公告)号：US06720212B2
公开(公告)日：2004-04-13
申请号：US10098840
申请日：2002-03-14
申请人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
发明人： Werner Robl , Thomas Goebel , Axel Christoph Brintzinger , Gerald Friese
IPC分类号： H01L2182
CPC分类号： H01L24/12 , H01L23/3114 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/05147 , H01L2224/05166 , H01L2224/05181 , H01L2224/05184 , H01L2224/05548 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/01033 , H01L2924/01068 , H01L2924/01073 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/01082 , H01L2924/01087 , H01L2924/01322 , H01L2924/014 , H01L2924/04941 , H01L2924/04953 , H01L2924/10253 , H01L2924/14 , H01L2924/19043 , H01L2924/00 , H01L2924/00014 , H01L2924/013
摘要： Disclosed is a method of ball grid array packaging, comprising the steps of providing a semiconductor die having a metal conductors thereon, covering said metal conductors with an insulative layer, etching through said insulative layer so as to provide one or more openings to said metal conductors, depositing a compliant material layer, etching through said compliant material layer so as to provide one or more openings to said metal conductors, depositing a substantially homogenous conductive layer, patterning said conductive layer so as to bring at least one of said metal conductors in electrical contact with one or more pads, each said pad comprising a portion of said conductive layer disposed upon said compliant material, and providing solder balls disposed upon said pads. Also disclosed is the apparatus made from the method.
摘要翻译：公开了一种球栅阵列封装的方法，包括以下步骤：提供其上具有金属导体的半导体管芯，用绝缘层覆盖所述金属导体，蚀刻穿过所述绝缘层，以便向所述金属导体提供一个或多个开口沉积柔性材料层，蚀刻穿过所述柔性材料层，以便向所述金属导体提供一个或多个开口;沉积基本上均匀的导电层;图案化所述导电层，以将所述金属导体中的至少一个导入电与一个或多个焊盘接触，每个所述焊盘包括设置在所述柔性材料上的所述导电层的一部分，以及设置在所述焊盘上的焊球。还公开了由该方法制成的装置。

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