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1. 发明授权

US09112053B2 Method for producing a semiconductor device including a dielectric layer 有权
标题翻译：用于制造包括电介质层的半导体器件的方法
公开(公告)号：US09112053B2
公开(公告)日：2015-08-18
申请号：US13537374
申请日：2012-06-29
申请人： Hans Weber , Franz Hirler , Andreas Meiser , Anton Mauder , Kurt Sorschag , Stefan Gamerith , Roman Knoefler
发明人： Hans Weber , Franz Hirler , Andreas Meiser , Anton Mauder , Kurt Sorschag , Stefan Gamerith , Roman Knoefler
IPC分类号： H01L21/8234 , H01L27/06 , H01L29/40 , H01L29/66 , H01L29/78 , H01L29/06
CPC分类号： H01L29/7802 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L27/0629 , H01L29/0653 , H01L29/407 , H01L29/66734 , H01L29/7828
摘要： A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.
摘要翻译：具有电介质层的半导体器件通过向半导体本体提供延伸到半导体本体中的第一沟槽，第一沟槽具有底部和侧壁来制造。第一电介质层形成在第一沟槽的下部的侧壁上，第一插塞形成在第一沟槽的下部，以覆盖第一电介质层。第一个塞子留下未覆盖的侧壁的上部。牺牲层形成在第一沟槽的上部的侧壁上，第二插塞形成在第一沟槽的上部。除去牺牲层以形成具有侧壁和底部的第二沟槽。第二介电层形成在第二沟槽中并延伸到第一介电层。

2. 发明申请

US20120083081A1 METHOD FOR PRODUCING A GATE ELECTRODE STRUCTURE 有权
标题翻译：生产门电极结构的方法
公开(公告)号：US20120083081A1
公开(公告)日：2012-04-05
申请号：US12894141
申请日：2010-09-30
申请人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
发明人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7803
摘要： A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.
摘要翻译：具有栅电极结构的晶体管通过提供具有第一表面的半导体本体和从第一表面沿半导体本体的垂直方向延伸的第一牺牲层来制造。通过在与第一表面相邻的部分中去除牺牲层来形成从第一表面延伸到半导体本体的第一沟槽。通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽。通过去除第二沟槽下方的第一牺牲层的至少一部分，在第二沟槽下方形成第三沟槽。形成介电层，其至少覆盖第三沟槽的侧壁并仅覆盖第二沟槽的侧壁。栅电极形成在第二沟槽中的电介质层上。第二沟槽中的栅电极和电介质层形成栅电极结构。

3. 发明授权

US08288230B2 Method for producing a gate electrode structure 有权
标题翻译：栅电极结构的制造方法
公开(公告)号：US08288230B2
公开(公告)日：2012-10-16
申请号：US12894141
申请日：2010-09-30
申请人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
发明人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7803
摘要： A transistor with a gate electrode structure is produced by providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface. A first trench extending from the first surface into the semiconductor body is formed by removing the sacrificial layer in a section adjacent the first surface. A second trench is formed by isotropically etching the semiconductor body in the first trench. A third trench is formed below the second trench by removing at least a part of the first sacrificial layer below the second trench. A dielectric layer is formed which at least covers sidewalls of the third trench and which only covers sidewalls of the second trench. A gate electrode is formed on the dielectric layer in the second trench. The gate electrode and dielectric layer in the second trench form the gate electrode structure.
摘要翻译：具有栅电极结构的晶体管通过提供具有第一表面的半导体本体和从第一表面沿半导体本体的垂直方向延伸的第一牺牲层来制造。通过在与第一表面相邻的部分中去除牺牲层来形成从第一表面延伸到半导体本体的第一沟槽。通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽。通过去除第二沟槽下方的第一牺牲层的至少一部分，在第二沟槽下方形成第三沟槽。形成介电层，其至少覆盖第三沟槽的侧壁并仅覆盖第二沟槽的侧壁。栅电极形成在第二沟槽中的电介质层上。第二沟槽中的栅电极和电介质层形成栅电极结构。

4. 发明授权

US08399325B2 Method for producing an electrode structure 有权
标题翻译：电极结构体的制造方法
公开(公告)号：US08399325B2
公开(公告)日：2013-03-19
申请号：US13240308
申请日：2011-09-22
申请人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
发明人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7803
摘要： A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure.
摘要翻译：一种用于制造具有电极结构的半导体器件的方法，包括：提供具有第一表面的半导体本体，以及从所述第一表面沿着所述半导体本体的垂直方向延伸的第一牺牲层，以及形成从所述第一表面延伸的第一沟槽表面进入半导体体。至少通过在与第一表面相邻的部分中去除牺牲层来形成第一沟槽。该方法还包括通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽，形成覆盖第二沟槽侧壁的电介质层，以及在第二沟槽，电极和电介质层中的电介质层上形成电极在形成电极结构的第二沟槽中。

5. 发明申请

US20130005099A1 METHOD FOR PRODUCING A SEMICONDUCTOR DEVICE INCLUDING A DIELECTRIC LAYER 有权
标题翻译：用于生产包括介电层的半导体器件的方法
公开(公告)号：US20130005099A1
公开(公告)日：2013-01-03
申请号：US13537374
申请日：2012-06-29
申请人： Hans Weber , Franz Hirler , Andreas Meiser , Anton Mauder , Kurt Sorschag , Stefan Gamerith , Roman Knoefler
发明人： Hans Weber , Franz Hirler , Andreas Meiser , Anton Mauder , Kurt Sorschag , Stefan Gamerith , Roman Knoefler
IPC分类号： H01L21/336 , H01L21/20
CPC分类号： H01L29/7802 , H01L21/823437 , H01L21/823481 , H01L21/823487 , H01L27/0629 , H01L29/0653 , H01L29/407 , H01L29/66734 , H01L29/7828
摘要： A semiconductor device with a dielectric layer is produced by providing a semiconductor body with a first trench extending into the semiconductor body, the first trench having a bottom and a sidewall. A first dielectric layer is formed on the sidewall in a lower portion of the first trench and a first plug is formed in the lower portion of the first trench so as to cover the first dielectric layer. The first plug leaves an upper portion of the sidewall uncovered. A sacrificial layer is formed on the sidewall in the upper portion of the first trench and a second plug is formed in the upper portion of the first trench. The sacrificial layer is removed so as to form a second trench having sidewalls and a bottom. A second dielectric layer is formed in the second trench and extends to the first dielectric layer.
摘要翻译：具有电介质层的半导体器件通过向半导体本体提供延伸到半导体本体中的第一沟槽，第一沟槽具有底部和侧壁来制造。第一电介质层形成在第一沟槽的下部的侧壁上，第一插塞形成在第一沟槽的下部，以覆盖第一电介质层。第一个塞子留下未覆盖的侧壁的上部。牺牲层形成在第一沟槽的上部的侧壁上，第二插塞形成在第一沟槽的上部。除去牺牲层以形成具有侧壁和底部的第二沟槽。第二介电层形成在第二沟槽中并延伸到第一介电层。

6. 发明申请

US20120083085A1 METHOD FOR PRODUCING AN ELECTRODE STRUCTURE 有权
标题翻译：生产电极结构的方法
公开(公告)号：US20120083085A1
公开(公告)日：2012-04-05
申请号：US13240308
申请日：2011-09-22
申请人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
发明人： Hans Weber , Stefan Gamerith , Roman Knoefler , Kurt Sorschag , Anton Mauder
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L29/0653 , H01L29/1095 , H01L29/407 , H01L29/4236 , H01L29/4238 , H01L29/66734 , H01L29/7803
摘要： A method for producing a semiconductor device with an electrode structure includes providing a semiconductor body with a first surface, and with a first sacrificial layer extending in a vertical direction of the semiconductor body from the first surface, and forming a first trench extending from the first surface into the semiconductor body. The first trench is formed at least by removing the sacrificial layer in a section adjacent to the first surface. The method further includes forming a second trench by isotropically etching the semiconductor body in the first trench, forming a dielectric layer which covers sidewalls of the second trench, and forming an electrode on the dielectric layer in the second trench, the electrode and the dielectric layer in the second trench forming the electrode structure.
摘要翻译：一种用于制造具有电极结构的半导体器件的方法，包括：提供具有第一表面的半导体本体，以及从所述第一表面沿着所述半导体本体的垂直方向延伸的第一牺牲层，以及形成从所述第一表面延伸的第一沟槽表面进入半导体体。至少通过在与第一表面相邻的部分中去除牺牲层来形成第一沟槽。该方法还包括通过在第一沟槽中各向同性蚀刻半导体本体来形成第二沟槽，形成覆盖第二沟槽侧壁的电介质层，以及在第二沟槽，电极和电介质层中的电介质层上形成电极在形成电极结构的第二沟槽中。

7. 发明申请

US20130075801A1 SELF-ADJUSTED CAPACITIVE STRUCTURE 审中-公开
标题翻译：自调整电容结构
公开(公告)号：US20130075801A1
公开(公告)日：2013-03-28
申请号：US13242842
申请日：2011-09-23
申请人： Hans Weber , Roman Knoefler , Kurt Sorschag
发明人： Hans Weber , Roman Knoefler , Kurt Sorschag
IPC分类号： H01L29/94 , H01L29/92 , H01L21/02
CPC分类号： H01L29/945 , H01L27/0733 , H01L29/4236 , H01L29/66181
摘要： A method for producing a capacitive structure in a semiconductor body includes forming a first trench in a first surface of the semiconductor body, forming a first dielectric layer on sidewalls and the bottom of the first trench, forming a first electrode layer on the first dielectric layer, forming at least one second trench by removing at least one part of the first dielectric layer to form a first gap in the first surface, and by widening the first gap, forming a second dielectric layer on sidewalls and the bottom of the at least one second trench, and forming a second electrode layer on the second dielectric layer.
摘要翻译：一种在半导体本体中制造电容结构的方法，包括在半导体本体的第一表面中形成第一沟槽，在第一沟槽的侧壁和底部上形成第一电介质层，在第一介电层上形成第一电极层通过去除所述第一介电层的至少一部分以在所述第一表面中形成第一间隙而形成至少一个第二沟槽，并且通过加宽所述第一间隙，在所述至少一个的侧壁和底部上形成第二电介质层并且在所述第二介电层上形成第二电极层。

8. 发明申请

US20070075381A1 Semiconductor memory device and method of production 失效
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20070075381A1
公开(公告)日：2007-04-05
申请号：US11241878
申请日：2005-09-30
申请人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
发明人： Stefano Parascandola , Roman Knoefler , Stephan Riedel , Dominik Olligs , Torsten Mueller , Dirk Caspary
IPC分类号： H01L29/76
CPC分类号： H01L27/115 , H01L27/11565 , H01L27/11568
摘要： The bit lines are produced by an implantation of a dopant by means of a sacrificial hard mask layer, which is later replaced with the gate electrodes formed of polysilicon in the memory cell array. Striplike areas of the memory cell array, which run transversely to the bit lines, are reserved by a blocking layer to be occupied by the bit line contacts. In these areas, the hard mask is used to form contact holes, which are self-aligned with the implanted buried bit lines. Between the blocked areas, the word lines are arranged normally to the bit lines.
摘要翻译：位线通过牺牲性硬掩模层的掺杂剂的注入而产生，牺牲性硬掩模层随后由存储单元阵列中由多晶硅形成的栅电极代替。横向于位线运行的存储单元阵列的条纹区域由阻塞层保留以被位线触点占据。在这些区域中，硬掩模用于形成与植入的掩埋位线自对准的接触孔。在阻塞区域之间，字线正常布置在位线上。

9. 发明申请

US20070045123A1 Methods of forming integrated circuit devices having metal interconnect layers therein 有权
标题翻译：形成其中具有金属互连层的集成电路器件的方法
公开(公告)号：US20070045123A1
公开(公告)日：2007-03-01
申请号：US11216686
申请日：2005-08-31
申请人： Duk Hong , Kyoung Lee , Markus Naujok , Roman Knoefler
发明人： Duk Hong , Kyoung Lee , Markus Naujok , Roman Knoefler
IPC分类号： C25D5/02
CPC分类号： C25D5/022 , H01L21/31144 , H01L21/76802 , H01L21/76877 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： Methods of forming metal interconnect layers include forming an electrically insulating layer having a contact hole therein, on a semiconductor substrate and then forming a recess in the electrically insulating layer, at a location adjacent the contact hole. The contact hole and the recess are then filled with a first electrically conductive material (e.g., tungsten (W)). At least a portion of the first electrically conductive material within the contact hole is then exposed. This exposure occurs by etching back a portion of the electrically insulating layer using the first electrically conductive material within the contact hole and within the recess as an etching mask. The first electrically conductive material within the recess is then removed to expose another portion of the electrically insulating layer. Following this, the exposed portion of the first electrically conductive material is covered with a second electrically conductive material (e.g., copper (Cu)), which directly contacts the exposed portion of the first electrically conductive material. This covering step results in the definition of a wiring pattern including the first and second electrically conductive materials.
摘要翻译：形成金属互连层的方法包括在半导体衬底上形成其中具有接触孔的电绝缘层，然后在邻近接触孔的位置在电绝缘层中形成凹陷。然后用第一导电材料（例如，钨（W））填充接触孔和凹部。然后露出接触孔内的第一导电材料的至少一部分。通过使用接触孔内部和凹部内的第一导电材料作为蚀刻掩模来蚀刻电绝缘层的一部分而发生该曝光。然后移除凹槽内的第一导电材料以露出电绝缘层的另一部分。之后，第一导电材料的暴露部分被直接接触第一导电材料的暴露部分的第二导电材料（例如铜（Cu））覆盖。该覆盖步骤导致包括第一和第二导电材料的布线图案的定义。

10. 发明授权

US08710620B2 Method of manufacturing semiconductor devices using ion implantation 有权
标题翻译：使用离子注入制造半导体器件的方法
公开(公告)号：US08710620B2
公开(公告)日：2014-04-29
申请号：US13552014
申请日：2012-07-18
申请人： Hans-Joachim Schulze , Johannes Laven , Dieter Fuchs , Werner Schustereder , Roman Knoefler
发明人： Hans-Joachim Schulze , Johannes Laven , Dieter Fuchs , Werner Schustereder , Roman Knoefler
IPC分类号： H01L21/425
CPC分类号： H01L29/0619 , H01L21/26513 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/1608 , H01L29/66068 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L29/8611
摘要： A manufacturing method provides a semiconductor device with a substrate layer and an epitaxial layer adjoining the substrate layer. The epitaxial layer includes first columns and second columns of different conductivity types. The first and second columns extend along a main crystal direction along which channeling of implanted ions occurs from a first surface into the epitaxial layer. A vertical dopant profile of one of the first and second columns includes first portions separated by second portions. In the first portions a dopant concentration varies by at most 30%. In the second portions the dopant concentration is lower than in the first portions. The ratio of a total length of the first portions to the total length of the first and second portions is at least 50%. The uniform dopant profiles improve device characteristics.
摘要翻译：制造方法为半导体器件提供衬底层和与衬底层相邻的外延层。外延层包括不同导电类型的第一列和第二列。第一和第二列沿着主晶体方向延伸，沿着主晶体方向，注入离子的沟道从第一表面发生到外延层中。第一和第二列之一的垂直掺杂剂分布包括由第二部分分开的第一部分。在第一部分中，掺杂剂浓度变化至多30％。在第二部分中，掺杂剂浓度低于第一部分。第一部分的总长度与第一和第二部分的总长度之比至少为50％。均匀的掺杂剂分布提高了器件特性。

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