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1. 发明授权

US07660180B2 Dielectric antifuse for electro-thermally programmable device 有权
标题翻译：用于电热可编程器件的介质反熔丝
公开(公告)号：US07660180B2
公开(公告)日：2010-02-09
申请号：US11720320
申请日：2005-11-24
申请人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
发明人： Hans M. B. Boeve , Karen Attenborough , Godefridus A. M. Hurkx , Prabhat Agarwal , Hendrik G. A. Huizing , Michael A. A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

2. 发明授权

US07839209B2 Tunnel field effect transistor 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US07839209B2
公开(公告)日：2010-11-23
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A. M. Hurkx , Radu Surdeanu , Gerben Doornbos
IPC分类号： H01L25/00
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

3. 发明申请

US20080144355A1 Dielectric Antifuse for Electro-Thermally Programmable Device 有权
标题翻译：电热可编程器件介质防腐剂
公开(公告)号：US20080144355A1
公开(公告)日：2008-06-19
申请号：US11720320
申请日：2005-11-24
申请人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
发明人： Hans M.B. Boeve , Karen Attenborough , Godefridus A.M. Hurkx , Prabhat Agarwal , Hendrik G.A. Huizing , Michael A.A. In'T Zandt , Jan W. Slotboom
IPC分类号： G11C17/18 , G11C11/00 , H01L21/326 , H01L29/02
CPC分类号： G11C11/5678 , G11C13/0004 , H01L27/2409 , H01L45/06 , H01L45/1233 , H01L45/1246 , H01L45/144
摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.
摘要翻译：热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径，用作编程材料的微小电加热器。由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。因此，编程功率可能很低。

4. 发明授权

US07709923B2 Metal-base nanowire transistor 失效
标题翻译：金属基纳米线晶体管
公开(公告)号：US07709923B2
公开(公告)日：2010-05-04
申请号：US12093790
申请日：2006-10-29
申请人： Prabhat Agarwal , Godefridus A. M. Hurkx
发明人： Prabhat Agarwal , Godefridus A. M. Hurkx
IPC分类号： H01L27/095
CPC分类号： H01L29/7606 , B82Y10/00 , H01L29/0665 , H01L29/0673 , Y10S977/936
摘要： A metal-base transistor is suggested. The transistor comprises a first and a second electrode (2, 6) and base electrode (6) to control current flow between the first and second electrode. The first electrode (2) is made from a semiconduction material. The base electrode (3) is a metal layer deposited on top of the semiconducting material forming the first electrode. According the invention the second electrode is formed by a semiconducting nanowire (6) being in electrical contact with the base electrode (3).
摘要翻译：建议使用金属晶体管。晶体管包括用于控制第一和第二电极之间的电流的第一和第二电极（2,6）和基极（6）。第一电极（2）由半导体材料制成。基极（3）是沉积在形成第一电极的半导体材料的顶部上的金属层。根据本发明，第二电极由与基极（3）电接触的半导体纳米线（6）形成。

5. 发明申请

US20080258182A1 Bicmos Compatible Jfet Device and Method of Manufacturing Same 审中-公开
标题翻译： Bicmos兼容Jfet设备及其制造方法相同
公开(公告)号：US20080258182A1
公开(公告)日：2008-10-23
申请号：US11577311
申请日：2005-10-13
申请人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
发明人： Prabhat Agarwal , Jan W. Slotboom , Wibo Van Noort
IPC分类号： H01L29/808 , H01L21/8232 , H01L21/337
CPC分类号： H01L27/098 , H01L21/8248 , H01L27/0623
摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.
摘要翻译：一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

6. 发明申请

US20100097135A1 TUNNEL FIELD EFFECT TRANSISTOR 有权
标题翻译：隧道场效应晶体管
公开(公告)号：US20100097135A1
公开(公告)日：2010-04-22
申请号：US12444140
申请日：2007-10-03
申请人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A.M. Hurkx , Radu Surdeanu
发明人： Gilberto Curatola , Prabhat Agarwal , Jan W. Slotboom , Godefridus A.M. Hurkx , Radu Surdeanu
IPC分类号： H03K3/353 , H01L29/78
CPC分类号： H01L29/161 , H01L29/165 , H01L29/7391
摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).
摘要翻译：隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。绝缘栅极（16）控制耗尽层的位置和厚度。该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

7. 发明授权

US07915709B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US07915709B2
公开(公告)日：2011-03-29
申请号：US11658228
申请日：2005-07-07
申请人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
发明人： Godefridus Adrianus Maria Hurkx , Prabhat Agarwal , Abraham Rudolf Balkenende , Petrus Hubertus Cornelis Magnee , Melanie Maria Hubertina Wagemans , Erik Petrus Antonius Maria Bakkers , Erwin Hijzen
IPC分类号： H01L29/66 , H01L21/8222
CPC分类号： H01L29/0804 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/0821 , H01L29/7378 , Y10S977/936
摘要： The invention relates to a semiconductor device (10) with a semiconductor body (12) comprising a bipolar transistor with an emitter region, a base region and a collector region (1, 2, 3) of, respectively, a first conductivity type, a second conductivity type opposite to the first conductivity type, and the first conductivity type. One of the emitter or collector regions (1, 3) comprises a nanowire (30). The base region (2) has been formed from a layer (20) at the surface of the semiconductor body (12); the other one (3, 1) of the emitter or collector regions (1, 3) has been formed in the semiconductor body (12) below the base region (2). The emitter or collector region (1, 3) comprising the nanowire (30) has been provided on the surface of the semiconductor body (12) such that its longitudinal axis extends perpendicularly to the surface.
摘要翻译：本发明涉及具有半导体本体（12）的半导体器件（10），该半导体器件（12）包括分别具有第一导电类型的发射极区，基极区和集电极区（1,2,3）的双极晶体管，与第一导电类型相反的第二导电类型和第一导电类型。发射极或集电极区域（1,3）中的一个包括纳米线（30）。基底区域（2）由半导体本体（12）表面的层（20）形成; 发射极或集电极区域（1,3）中的另一个（3,1）已经形成在基极区域（2）下方的半导体本体（12）中。包括纳米线（30）的发射极或集电极区域（1,3）已经设置在半导体本体（12）的表面上，使得其纵向轴线垂直于该表面延伸。

8. 发明授权

US07791108B2 Nanowire tunneling transistor 失效
标题翻译：纳米线隧道晶体管
公开(公告)号：US07791108B2
公开(公告)日：2010-09-07
申请号：US12161574
申请日：2007-01-24
申请人： Fred Hurkx , Prabhat Agarwal
发明人： Fred Hurkx , Prabhat Agarwal
IPC分类号： H01L21/336 , H01L21/8235
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

9. 发明授权

US07538593B2 Circuit and method to convert a single ended signal to duplicated signals 有权
标题翻译：将单端信号转换为重复信号的电路和方法
公开(公告)号：US07538593B2
公开(公告)日：2009-05-26
申请号：US11710270
申请日：2007-02-23
申请人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
发明人： Prabhat Agarwal , Mayank Goel , Pradip Mandal
IPC分类号： G06F1/04
CPC分类号： H03K5/151
摘要： A circuit to convert a single ended signal to differential signals is disclosed. The circuit has two paths with each of the two paths comprising a plurality of stages. The number of stages in each of the two paths is the same. A first path of the two paths includes a buffer stage and at least one inverter stage. A second path of the two paths includes at least two inverter stages. The buffer stage has a delay matched to that of a first inverter stage of the second path. The buffer stage comprises a first pair of transistors comprising a first transistor of a first category operatively connected to a first transistor of a second category with their channel connections being connected in series.
摘要翻译：公开了将单端信号转换为差分信号的电路。该电路具有两条路径，其中两条路径中的每条路径包括多个级。两个路径中的每个路段的数量是相同的。两个路径的第一路径包括缓冲段和至少一个逆变器级。两路径的第二路径包括至少两个逆变器级。缓冲级具有与第二路径的第一反相器级的延迟匹配的延迟。缓冲级包括第一对晶体管，其包括第一类别的第一晶体管，其可操作地连接到第二类别的第一晶体管，其沟道连接串联连接。

10. 发明申请

US20090008631A1 NANOWIRE TUNNELING TRANSISTOR 失效
标题翻译： NANOWIRE隧道晶体管
公开(公告)号：US20090008631A1
公开(公告)日：2009-01-08
申请号：US12161574
申请日：2007-01-24
申请人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
发明人： Godefridus Andrianus Maria Hurkx , Prabhat Agarwal
IPC分类号： H01L29/06
CPC分类号： H01L29/1054 , B82Y10/00 , H01L29/0665 , H01L29/0673 , H01L29/0676 , H01L29/068 , H01L29/66666 , H01L29/7827 , Y10S977/75 , Y10S977/813 , Y10S977/938
摘要： A transistor comprises a nanowire (22, 22′) having a source (24) and a drain (29) separated by an intrinsic or lowly doped region (26, 28). A potential barrier is formed at the interface of the intrinsic or lowly doped region (26, 28) and one of the source (24) and the drain (29). A gate electrode (32) is provided in the vicinity of the potential barrier such that the height of the potential barrier can be modulated by applying an appropriate voltage to the gate electrode (32).
摘要翻译：晶体管包括具有由本征或低掺杂区域（26,28）分开的源极（24）和漏极（29）的纳米线（22,22'）。在本征或低掺杂区域（26,28）和源极（24）和漏极（29）中的一个的界面处形成势垒。在势垒附近设置栅电极（32），使得可以通过向栅极（32）施加适当的电压来调制势垒的高度。

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