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1. 发明授权

US08796150B2 Bilayer trench first hardmask structure and process for reduced defectivity 有权
标题翻译：双层沟槽第一硬掩模结构和减少缺陷的过程
公开(公告)号：US08796150B2
公开(公告)日：2014-08-05
申请号：US13012166
申请日：2011-01-24
申请人： Hakeem B. S. Akinmade-Yusuff , Samuel Sung Shik Choi , Edward R. Engbrecht , John A. Fitzsimmons
发明人： Hakeem B. S. Akinmade-Yusuff , Samuel Sung Shik Choi , Edward R. Engbrecht , John A. Fitzsimmons
IPC分类号： H01L21/311 , H01L21/32 , H01L29/06
CPC分类号： H01L21/31144 , H01L21/76804 , H01L21/76807
摘要： A method and structure for transferring a lithographic pattern into a substrate includes forming a dielectric hardmask layer over a dielectric substrate. A metal hardmask layer is formed over the dielectric hardmask layer. A protective capping hardmask layer or capping film is formed over the metal hardmask layer, and a lithographic structure for pattern transfer is formed over the capping layer. A pattern is transferred into the dielectric substrate using the defined lithographic structure. The capping hardmask layer can be removed during subsequent processing.
摘要翻译：用于将光刻图案转印到基板中的方法和结构包括在电介质基底上形成电介质硬掩模层。在介电硬掩模层上形成金属硬掩模层。在金属硬掩模层上形成保护性覆盖硬掩模层或覆盖膜，并且在覆盖层上形成用于图案转印的光刻结构。使用限定的光刻结构将图案转移到电介质基板中。在后续处理过程中，可以移除加盖硬掩模层。

2. 发明授权

US08287980B2 Edge protection seal for bonded substrates 失效
标题翻译：粘合基材的边缘保护密封
公开(公告)号：US08287980B2
公开(公告)日：2012-10-16
申请号：US12608363
申请日：2009-10-29
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： B32B1/04 , B32B38/00
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

3. 发明授权

US08138093B2 Method for forming trenches having different widths and the same depth 有权
标题翻译：用于形成具有不同宽度和相同深度的沟槽的方法
公开(公告)号：US08138093B2
公开(公告)日：2012-03-20
申请号：US12539930
申请日：2009-08-12
申请人： Hakeem B. S. Akinmade-Yusuff , Samuel S. Choi
发明人： Hakeem B. S. Akinmade-Yusuff , Samuel S. Choi
IPC分类号： H01L21/311
CPC分类号： H01L21/31144 , H01L21/0335 , H01L21/3085 , H01L21/31138
摘要： A lithographic material stack including a photo-resist and an organic planarizing layer is combined with an etch process that generates etch residues over a wide region from sidewalls of etched regions. By selecting the etch chemistry that produces deposition of etch residues from the organic planarizing layer over a wide region, the etch residue generated at the sidewalls of the wide trench is deposited over the entire bottom surface of the wide trench. An etch residue portion remains at the bottom surface of the wide trench when the organic planarizing layer is etched through in the first trench region. The etch residue portion is employed in the next step of the etch process to retard the etch rate in the wide trench, thereby producing the same depth for all trenches in the material layer into which the pattern of the lithographic material stack is transferred.
摘要翻译：包括光致抗蚀剂和有机平坦化层的平版印刷材料堆叠与在蚀刻区域的侧壁的宽区域上产生蚀刻残留物的蚀刻工艺组合。通过选择在宽的区域上产生来自有机平坦化层的蚀刻残留物沉积的蚀刻化学物质，在宽沟槽的侧壁处产生的蚀刻残留物沉积在宽沟槽的整个底表面上。当在第一沟槽区域中蚀刻有机平坦化层时，蚀刻残留部分保留在宽沟槽的底表面。蚀刻残留部分用于蚀刻工艺的下一步骤以延迟宽沟槽中的蚀刻速率，从而为材料层中所有的平版印刷材料堆叠的图案被转移到其中的所有沟槽产生相同的深度。

4. 发明授权

US08030157B1 Liner protection in deep trench etching 失效
标题翻译：衬里保护深沟蚀刻
公开(公告)号：US08030157B1
公开(公告)日：2011-10-04
申请号：US12782050
申请日：2010-05-18
申请人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Habib Hichri , Ahmad D. Katnani , Kaushik A. Kumar , Narender Rana , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： H01L21/8242
CPC分类号： H01L21/76232
摘要： A method of forming a trench in a semiconductor device formed of a substrate and a first layer formed over the substrate includes forming an initial trench that passes through the first layer to the substrate, the initial trench having a diameter that decreases from a first diameter to a second diameter, the second diameter being measured at a distance closer to the substrate than the first diameter; exposing the trench to a dopant via an orthogonal ion implant to form doped regions sidewalls of the trench; and etching the trench to remove at least some of the doped regions.
摘要翻译：在由衬底和形成在衬底上的第一层形成的半导体器件中形成沟槽的方法包括形成通过第一层到衬底的初始沟槽，初始沟槽的直径从第一直径减小到第二直径，第二直径在比第一直径更靠近基板的距离处被测量; 通过正交离子注入将沟槽暴露于掺杂剂以形成沟槽的掺杂区域侧壁; 并蚀刻沟槽以去除至少一些掺杂区域。

5. 发明授权

US08679611B2 Edge protection seal for bonded substrates 有权
标题翻译：粘合基材的边缘保护密封
公开(公告)号：US08679611B2
公开(公告)日：2014-03-25
申请号：US13556369
申请日：2012-07-24
申请人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
发明人： Mukta G. Farooq , Emily Kinser , Richard S. Wise , Hakeem B. S. Akinmade-Yusuff
IPC分类号： B32B3/02 , B29C65/48
CPC分类号： H01L21/02263 , H01L21/187 , H01L21/76898 , H01L25/074 , H01L25/50 , H01L2924/0002 , H01L2924/00
摘要： A dielectric material layer is deposited on exposed surfaces of a bonded structure that includes a first substrate and a second substrate. The dielectric material layer is formed on an exposed planar surface of a second substrate and the entirety of peripheral sidewalls of the first and second substrates. The dielectric material layer can be formed by chemical vapor deposition, atomic layer deposition, or plasma induced deposition. Further, the dielectric material layer seals the entire periphery of the interface between the first and second substrates. If a planar portion of the dielectric material layer can be removed by planarization to facilitate thinning of the bonded structure, the remaining portion of the dielectric material layer can form a dielectric ring.
摘要翻译：介电材料层沉积在包括第一基板和第二基板的接合结构的暴露表面上。介电材料层形成在第二基板的暴露的平坦表面和第一和第二基板的整个周边侧壁上。介电材料层可以通过化学气相沉积，原子层沉积或等离子体诱导沉积形成。此外，介电材料层密封第一和第二基板之间的界面的整个周边。如果可以通过平坦化去除电介质材料层的平面部分以便于键合结构的薄化，则介电材料层的剩余部分可以形成介电环。

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