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1. 发明授权

US07688302B2 Shift register and display device using same 有权
公开(公告)号：US07688302B2
公开(公告)日：2010-03-30
申请号：US11543218
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

2. 发明授权

US07733321B2 Shift register and display device using same 有权
标题翻译：移位寄存器和显示设备使用相同
公开(公告)号：US07733321B2
公开(公告)日：2010-06-08
申请号：US11543219
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
摘要翻译：移位寄存器包括多级触发器。作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

3. 发明申请

US20070242021A1 Level shifter circuit and display device provided therewith 有权
公开(公告)号：US20070242021A1
公开(公告)日：2007-10-18
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.

4. 发明授权

US06996203B2 Bidirectional shift register and display device incorporating same 失效
标题翻译：双向移位寄存器和包含其的显示装置
公开(公告)号：US06996203B2
公开(公告)日：2006-02-07
申请号：US10860660
申请日：2004-06-04
申请人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
发明人： Mamoru Onda , Hajime Washio , Shunsuke Hayashi , Hiroshi Murofushi , Nobuhiko Suzuki
IPC分类号： G11C19/00
CPC分类号： G06F5/01 , G09G3/006 , G09G3/20 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0289 , G09G2330/12
摘要： The present invention includes: a shift register section, including multiple-stage flip-flops operating in synchronism with a clock signal, for switching a shift direction in accordance with an externally supplied direction instruct signal; a waveform change section for changing in waveform a signal output of one of the flip-flops which is in a first predetermined stage; and an inspection signal switching section for switching, in accordance with the direction instruct signal, an output between the signal output which has been changed in waveform in the waveform change section and a signal output of one of the flip-flops which is in a second predetermined stage.
摘要翻译：本发明包括：移位寄存器部分，包括与时钟信号同步操作的多级触发器，用于根据外部提供的方向指示信号切换移位方向; 波形变化部分，用于改变处于第一预定阶段的触发器之一的信号输出的波形; 以及检查信号切换部，根据方向指示信号，切换波形变化部中波形变化的信号输出与第二个触发器中的一个触发器的信号输出之间的输出预定阶段。

5. 发明授权

US08248348B2 Level shifter circuit and display device provided therewith 有权
标题翻译：电平移位电路和显示装置
公开(公告)号：US08248348B2
公开(公告)日：2012-08-21
申请号：US11812461
申请日：2007-06-19
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Shunsuke Hayashi
IPC分类号： H03K19/0175 , H03L5/00 , G09G5/00 , G09G3/28 , G09G3/36
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
摘要翻译：电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

6. 发明授权

US07289097B2 Scanning direction control circuit and display device 有权
标题翻译：扫描方向控制电路和显示装置
公开(公告)号：US07289097B2
公开(公告)日：2007-10-30
申请号：US10702077
申请日：2003-11-06
申请人： Seijirou Gyouten , Sachio Tsujino , Hajime Washio , Eiji Matsuda , Keiichi Ina , Yuhichiroh Murakami , Shunsuke Hayashi , Mamoru Onda
发明人： Seijirou Gyouten , Sachio Tsujino , Hajime Washio , Eiji Matsuda , Keiichi Ina , Yuhichiroh Murakami , Shunsuke Hayashi , Mamoru Onda
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G3/3677 , G09G2310/0283 , G09G2310/0289 , G11C19/00 , G11C19/28
摘要： The subject invention discloses a scanning direction control circuit, which includes a bidirectional shift register in which shifting direction is switched in accordance with a switching signal L/R, which is step-upped by a level shifter when having lower amplitude than the driving voltage. The scanning direction control circuit includes a latch circuit between the level shifter and the bidirectional shift register, and a control circuit causes the latch circuit to carry out latching operation after shifting operation of flip-flops constituting the bidirectional shift register is completed in response to output signals of the flip-flops. The control circuit brings the level shifter into active state in a period before, at and after the latching timing, and brings the level shifter into inactive state in the remaining period. With this arrangement, the switching signal L/R can be supplied at a predetermined timing regardless of external input timing thereof, with low power consumption.
摘要翻译：本发明公开了一种扫描方向控制电路，其包括双向移位寄存器，其中根据切换信号L / R切换移位方向，当切换信号L / R在比驱动电压低的振幅时由电平移位器升压。扫描方向控制电路包括电平移位器和双向移位寄存器之间的锁存电路，并且控制电路使得锁存电路在构成双向移位寄存器的触发器的移位操作之后响应于输出而完成锁存操作触发器的信号。控制电路在锁存定时之前，之后和之后的时段中使电平移位器进入有效状态，并且在剩余时间段内使电平移位器进入非活动状态。利用这种布置，可以在低功耗的情况下以预定的时序提供开关信号L / R，而不管其外部输入定时。

7. 发明授权

US07248243B2 Level shifter circuit and display device provided therewith 有权
标题翻译：电平移位电路和显示装置
公开(公告)号：US07248243B2
公开(公告)日：2007-07-24
申请号：US10438886
申请日：2003-05-16
申请人： Yuhichiroh Murakami , Seijirou Gyouten , Shunsuke Hayashi , Hajime Washio , Eiji Matsuda , Sachio Tsujino
发明人： Yuhichiroh Murakami , Seijirou Gyouten , Shunsuke Hayashi , Hajime Washio , Eiji Matsuda , Sachio Tsujino
IPC分类号： H03K19/0175 , H03L5/00 , G09G3/28 , G09G3/36 , G09G5/00
CPC分类号： G09G3/3611 , G09G2300/0408 , G09G2310/0289 , H03K19/0013 , H03K19/018521
摘要： A level shift circuit includes first and second level shifters which respectively output first and second output signals that are produced by level shifting two kinds of input clock signals whose high level periods do not overlap. The level shift circuit also includes control transistors and control lines which, together, prevent a feedthrough current from flowing into the second level shifter when the first output signal is high level, and prevent a feedthrough current from flowing into the first level shifter when the second output signal is high level, so as to suspend the level shift operation of the first and second level shifters. With the level shift circuit, power consumption during a specific time period in a non-active period of the clock signal can be eliminated, where the specific time period of one clock signal is the active period of the other clock signal.
摘要翻译：电平移位电路包括第一和第二电平移位器，其分别输出通过电平移位高电平周期不重叠的两种输入时钟信号产生的第一和第二输出信号。电平移位电路还包括控制晶体管和控制线，其一起在第一输出信号为高电平时防止馈通电流流入第二电平移位器，并且当第二电平移位器第二输出信号为高电平时，防止馈通电流流入第一电平移位器输出信号是高电平，以便暂停第一和第二电平移位器的电平移位操作。利用电平移位电路，可以消除在时钟信号的非有效周期中的特定时间段内的功率消耗，其中一个时钟信号的特定时间周期是另一个时钟信号的有效周期。

8. 发明申请

US20070024567A1 Shift register and display device using same 有权
标题翻译：移位寄存器和显示设备使用相同
公开(公告)号：US20070024567A1
公开(公告)日：2007-02-01
申请号：US11543218
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.
摘要翻译：移位寄存器包括多级触发器。作为其前一触发器的最后级触发器Fn和触发器Fn-1通过向其输入来自最后级触发器的输出信号而被复位。在用于输出输出信号的最后级触发器的输出端Q和用于接收输出信号的最后级触发器的输入端R之间提供延迟装置，用于延迟输出的输入信号到输入端R.触发器Fn在同一时间或在先前的触发器Fn-1复位之后复位。通过这种布置，可以防止由于不能重置触发器而引起的电路故障。

9. 发明授权

US07274351B2 Driver circuit and shift register of display device and display device 有权
标题翻译：显示设备和显示设备的驱动电路和移位寄存器
公开(公告)号：US07274351B2
公开(公告)日：2007-09-25
申请号：US10446149
申请日：2003-05-28
申请人： Hajime Washio , Shunsuke Hayashi
发明人： Hajime Washio , Shunsuke Hayashi
IPC分类号： G09G3/36
CPC分类号： G09G3/3688 , G09G2310/0248
摘要： A driver circuit for a display device includes a plurality of set-reset flip-flops and switch circuits, and is arranged so that a timing pulse for sampling outputted from the flip-flop is supplied to the switch circuit, so as to cause the switch circuit to receive a clock signal. The clock signal operates as a set signal of the next stage flip-flop and outputted as a control signal for carrying out pre-charging of a data signal line and a selected pixel connected to the data signal line, with a switch. Thus, in case of performing pre-charging of a signal supplying line with an internal pre-charging circuit by using a pre-charging power source having small driving ability, this arrangement can provide a driver circuit for a display device capable of preventing fluctuation of a signal supplied to a different signal supplying line, while keeping the circuit scale of the shift register small.
摘要翻译：用于显示装置的驱动器电路包括多个设定复位触发器和开关电路，并且被布置成使得从触发器输出的用于采样的定时脉冲被提供给开关电路，以便使开关电路接收时钟信号。时钟信号作为下一级触发器的设定信号工作，并作为控制信号输出，用于通过开关对数据信号线和连接到数据信号线的选择像素进行预充电。因此，在通过使用具有小驱动能力的预充电电源来对信号供给线进行内部预充电电路的预充电的情况下，可以提供能够防止波动的显示装置的驱动电路在保持移位寄存器的电路规模的同时，提供给不同信号供给线路的信号。

10. 发明申请

US20070024568A1 Shift register and display device using same 有权
公开(公告)号：US20070024568A1
公开(公告)日：2007-02-01
申请号：US11543219
申请日：2006-10-05
申请人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
发明人： Shunsuke Hayashi , Seijirou Gyouten , Hajime Washio , Eiji Matsuda , Sachio Tsujino , Yuichiro Murakami
IPC分类号： G09G3/36
CPC分类号： G11C19/00 , G09G3/20 , G09G2300/08 , G09G2310/0267 , G09G2310/0275 , G09G2310/0283 , G09G2310/0286 , G09G2310/08 , G11C19/28
摘要： A shift register includes plural stages of flip-flops. The last-stage flip-flop Fn and the flip-flop Fn−1 that is the preceding flip-flop thereof are reset by inputting thereto an output signal from the last-stage flip-flop. A delaying means is provided, between an output terminal Q of the last-stage flip-flop for outputting the output signal and an input terminal R of the last-stage flip-flop for receiving the output signal, for delaying an input of the output signal to the input terminal R. The flip-flop Fn is reset at same time or after the preceding flip-flop Fn−1 is reset. With this arrangement, it is possible to prevent malfunctions of circuits due to a failure to reset the flip-flops.

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