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1. 发明授权

US4503315A Semiconductor device with fuse 失效
标题翻译：带保险丝的半导体器件
公开(公告)号：US4503315A
公开(公告)日：1985-03-05
申请号：US453099
申请日：1982-12-27
申请人： Hajime Kamioka , Mikio Takagi , Noriaki Sato , Motoo Nakano , Takashi Iwai
发明人： Hajime Kamioka , Mikio Takagi , Noriaki Sato , Motoo Nakano , Takashi Iwai
IPC分类号： G11C17/06 , G11C17/14 , H01L21/82 , H01L23/525 , H01L27/10 , H01L23/52
CPC分类号： H01L23/5258 , H01L2924/0002
摘要： A semiconductor device with a fuse including an insulating layer having at least one step. A fusible film on the insulating layer crosses the step and a covering film is formed on the fusible film, the step and the insulating layer. When the portion of the fusible film crossing the step is irradiated with a laser beam the portion of the fusible film on the upper surface of the insulating layer melts and flows onto the lower surface of the insulating layer without forming a hole, thereby separating the fusible film at the step.
摘要翻译：一种具有熔丝的半导体器件，包括具有至少一个台阶的绝缘层。绝缘层上的可熔薄膜穿过该步骤，并且在可熔膜，台阶和绝缘层上形成覆盖膜。当穿过该台阶的可熔膜的部分被激光束照射时，绝缘层上表面上的可熔膜的部分熔化并流到绝缘层的下表面，而不形成孔，从而将可熔体电影在一步。

2. 发明授权

US4375993A Method of producing a semiconductor device by simultaneous multiple laser annealing 失效
标题翻译：通过同时进行多次激光退火制造半导体器件的方法
公开(公告)号：US4375993A
公开(公告)日：1983-03-08
申请号：US252216
申请日：1981-04-08
申请人： Haruhisa Mori , Hajime Kamioka , Motoo Nakano , Nobuo Sasaki
发明人： Haruhisa Mori , Hajime Kamioka , Motoo Nakano , Nobuo Sasaki
IPC分类号： H01L29/78 , H01L21/20 , H01L21/208 , H01L21/263 , H01L21/268 , H01L21/321 , H01L21/324 , H01L21/265
CPC分类号： H01L21/321 , H01L21/02488 , H01L21/02532 , H01L21/02683 , H01L21/02686 , H01L21/02691 , H01L21/268 , Y10S148/09 , Y10S148/091 , Y10S148/093 , Y10S148/123
摘要： A method of producing a semiconductor device which comprises steps of forming an insulator layer on a semiconductor substrate, forming a semiconductor layer on the insulator layer and then annealing the semiconductor layer by means of a first laser with a second laser being applied to the insulator layer to heat it while the first layer is applied to the semiconductor laser.
摘要翻译：一种制造半导体器件的方法，包括以下步骤：在半导体衬底上形成绝缘体层，在绝缘体层上形成半导体层，然后借助第一激光器对半导体层进行退火，第二激光被施加到绝缘体层以在将第一层施加到半导体激光器时加热它。

3. 发明授权

US5670885A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US5670885A
公开(公告)日：1997-09-23
申请号：US475504
申请日：1995-06-07
申请人： Takashi Iwai , Motoo Nakano
发明人： Takashi Iwai , Motoo Nakano
IPC分类号： H01L27/02 , G01R27/00
CPC分类号： H01L27/0248
摘要： A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).
摘要翻译：半导体器件具有第一导电型半导体衬底（19），包括形成在第二导电型半导体层（20）中的垂直双极晶体管（18）的内部电路和保护元件（14）。保护元件包括形成在设置在半导体衬底（19）上的第二导电型半导体层（20a）的上部的第一导电型扩散层（22a）和第二导电型扩散层（27,30）形成在第一导电型扩散层（22a）中。扩散层（27,30）至少部分地比垂直双极晶体管（18）的发射极扩散层（23）更深。

4. 发明授权

US5648676A Semiconductor device with protective element 失效
标题翻译：具有保护元件的半导体器件
公开(公告)号：US5648676A
公开(公告)日：1997-07-15
申请号：US591955
申请日：1996-01-23
申请人： Takashi Iwai , Motoo Nakano
发明人： Takashi Iwai , Motoo Nakano
IPC分类号： H01L27/02 , H01L29/00
CPC分类号： H01L27/0248
摘要： A semiconductor device has a first-conduction-type semiconductor substrate (19), an internal circuit including a vertical bipolar transistor (18) formed in a second-conduction-type semiconductor layer (20), and a protective element (14). The protective element comprises a first-conduction-type diffusion layer (22a) formed at an upper part of a second-conduction-type semiconductor layer (20a) disposed on the semiconductor substrate (19), and a second-conduction-type diffusion layer (27, 30) formed in the first-conduction-type diffusion layer (22a). The diffusion layer (27, 30) is at least partly deeper than an emitter diffusion layer (23) of the vertical bipolar transistor (18).
摘要翻译：半导体器件具有第一导电型半导体衬底（19），包括形成在第二导电型半导体层（20）中的垂直双极晶体管（18）的内部电路和保护元件（14）。保护元件包括形成在设置在半导体衬底（19）上的第二导电型半导体层（20a）的上部的第一导电型扩散层（22a）和第二导电型扩散层（27,30）形成在第一导电型扩散层（22a）中。扩散层（27,30）至少部分地比垂直双极晶体管（18）的发射极扩散层（23）更深。

5. 发明授权

US4275093A Method of manufacturing insulated gate semiconductor devices by high pressure thermal oxidation with water vapor 失效
标题翻译：用水蒸气高压热氧化制造绝缘栅半导体器件的方法
公开(公告)号：US4275093A
公开(公告)日：1981-06-23
申请号：US048069
申请日：1979-06-13
申请人： Nobuo Sasaki , Yasuo Kobayashi , Ryoiku Tohgei , Takashi Iwai , Motoo Nakano
发明人： Nobuo Sasaki , Yasuo Kobayashi , Ryoiku Tohgei , Takashi Iwai , Motoo Nakano
IPC分类号： H01L27/12 , H01L21/316 , H01L21/762 , H01L21/86 , H01L29/78
CPC分类号： H01L21/02238 , H01L21/02255 , H01L21/31662 , H01L21/76264 , H01L21/76281 , Y10S438/909
摘要： A method of manufacturing SOS type semiconductor devices having small leakage current comprising the steps of forming a single crystal semiconductor film on an insulator single crystal substrate, selectively forming a film for masking against oxidation on the surface of the single crystal semiconductor film, and thermally oxidizing the single crystal semiconductor film, in a region which is not covered with the masking film, down to the surface of the insulating single crystal substrate in a water vapor atmosphere having a high pressure which is at least more than atmospheric pressure.
摘要翻译：一种制造具有小的漏电流的SOS型半导体器件的方法，包括以下步骤：在绝缘体单晶衬底上形成单晶半导体膜，在单晶半导体膜的表面上选择性地形成用于掩蔽抗氧化的膜，以及热氧化在没有被掩模膜覆盖的区域中的单晶半导体膜在具有至少大于大气压的高压的水蒸汽气氛中向下到达绝缘单晶基板的表面。

6. 发明授权

US4262340A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4262340A
公开(公告)日：1981-04-14
申请号：US92858
申请日：1979-11-09
申请人： Nobuo Sasaki , Yasuo Kobayashi , Takashi Iwai , Motoo Nakano
发明人： Nobuo Sasaki , Yasuo Kobayashi , Takashi Iwai , Motoo Nakano
IPC分类号： G11C11/41 , G11C5/06 , G11C8/08 , G11C11/408 , G11C11/412 , G11C11/418 , H01L27/11 , G11C11/40
CPC分类号： G11C11/418 , G11C11/4085 , G11C11/412 , G11C5/063 , G11C8/08 , H01L27/1104 , H01L27/1108
摘要： A semiconductor memory device provides a plurality of bit lines, a plurality of memory cells each of which is connected to a pair of different bit lines, a plurality of common word wires each of which is connected to the memory cells via a transmission gate. A characteristic feature of the present invention is to provide at least one amplifier between two memory cells which are connected to a word line or a bit line so as to prevent an increase of the access time of the memory device.
摘要翻译：半导体存储器件提供多个位线，多个存储单元，每个存储单元都连接到一对不同的位线，多个公共字线，每个通常的字线经由传输门连接到存储单元。本发明的特征在于提供连接到字线或位线的两个存储单元之间的至少一个放大器，以防止存储器件的访问时间的增加。

7. 发明授权

US5888633A Micro-structures having structural members capable of withstanding permanent bend 失效
标题翻译：具有能够承受永久弯曲的结构构件的微结构
公开(公告)号：US5888633A
公开(公告)日：1999-03-30
申请号：US820359
申请日：1997-03-12
申请人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
发明人： Motoo Nakano , Hiroshi Nomura , Masaya Katayama , Toshimi Ikeda , Fumihiko Inoue , Junichi Ishikawa , Masahiro Kuwamura
IPC分类号： B81B3/00 , H01L21/02 , H01L21/20 , H01L21/306 , B32B7/02
CPC分类号： B81B3/0005 , B81C1/0092 , H01L21/02063 , H01L28/87 , Y10T428/24744 , Y10T428/24942 , Y10T428/26 , Y10T428/8305
摘要： A micro-structure including at least a first bendable member having first and second ends and being supported at the first end only, and either being spaced from a rigid component, or being spaced from a second bendable member also supported only at a first end thereof. The first member has a length L from the first end to the second end specified by one of the following equations: (a) for the first member adjacent to the rigid component: L
摘要翻译：一种微结构，包括至少第一可弯曲构件，其具有第一端和第二端，仅在第一端处被支撑，并且与刚性构件间隔开，或者与第二可弯曲构件间隔开，第二可弯曲构件也仅在其第一端处支撑。第一构件具有从以下等式之一指定的第一端至第二端的长度L：（a）对于与刚性构件相邻的第一构件：L <（2Edt3 / 3P）+ E，fra 1/4 + EE，其中E是第一构件的材料的杨氏模量; d是第一构件和刚性构件之间的空间的距离; t是第一构件的厚度; 并且P是施加到所述第一构件的外部压力; 或b）对于与第二构件相邻的第一构件：L <（2Ed't3 / 3P）+ E，fra 1/4 + EE，其中E，t和P如上所定义; 并且d'是第一和第二构件之间的空间的距离。

8. 发明授权

US4541074A Semiconductor device for memory cell 失效
标题翻译：用于存储单元的半导体器件
公开(公告)号：US4541074A
公开(公告)日：1985-09-10
申请号：US393118
申请日：1982-06-28
申请人： Motoo Nakano
发明人： Motoo Nakano
IPC分类号： G11C17/00 , G11C17/12 , H01L21/8229 , H01L21/8246 , H01L27/102 , H01L27/112 , H01L29/78 , G11C11/40
CPC分类号： H01L27/112 , G11C17/12
摘要： A ROM including memory cells having characteristics corresponding to the "1" or "0" information to be stored, the correspondence to "1" or "0" information being achieved by changing the conductivity type of at least a portion of a semiconductor layer in the semiconductor devices of the memory cells.
摘要翻译：包括具有与要存储的“1”或“0”信息对应的特征的存储单元的ROM，通过改变半导体层的至少一部分的导电类型来实现与“1”或“0”信息的对应关系存储单元的半导体器件。

9. 发明授权

US4350536A Method of producing dynamic random-access memory cells 失效
标题翻译：生成动态随机存取存储单元的方法
公开(公告)号：US4350536A
公开(公告)日：1982-09-21
申请号：US180947
申请日：1980-08-25
申请人： Motoo Nakano , Tsutomu Ogawa
发明人： Motoo Nakano , Tsutomu Ogawa
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/78 , H01L21/02 , H01L21/18 , H01L21/22 , H01L21/265
CPC分类号： H01L27/1085 , H01L27/10805
摘要： The invention is concerned with an improved method of producing a one-transistor cell for a dynamic RAM having a capacitor plate, a transfer gate and a shallow n.sup.+ -type region and a deeper p.sup.+ -type region for a junction capacitance. After formation of a thin oxide layer of a dielectric for an MOS capacitance, a patterned photo resist layer is formed. Using the photo resist layer as a mask, n-type impurities are doped into a semiconductor substrate. The capacitor plate and a masking layer are deposited on the photo resist layer and the thin oxide layer. P-type impurities are doped into the capacitor plate. Then, portions of the capacitor plate and masking layer on the photo resist layer are removed by removing the photo resist layer. An end portion of the capacitor plate is removed from under an edge of the remaining masking layer by etching. The p-type impurities are diffused into the silicon substrate by heating to form the deeper p.sup.+ -type region which does not extend beyond the n.sup.+ -type region.
摘要翻译：本发明涉及一种用于动态RAM的单晶体管单元的改进方法，其具有用于结电容的电容器板，传输栅极和浅n +型区域和较深p +型区域。在形成用于MOS电容的电介质的薄氧化物层之后，形成图案化的光致抗蚀剂层。使用光致抗蚀剂层作为掩模，将n型杂质掺杂到半导体衬底中。电容器板和掩模层沉积在光致抗蚀剂层和薄氧化物层上。 P型杂质被掺杂到电容器板中。然后，通过除去光致抗蚀剂层来除去光致抗蚀剂层上的电容器板和掩模层的部分。电容器板的端部通过蚀刻从剩下的掩模层的边缘下方去除。 p型杂质通过加热扩散到硅衬底中以形成不延伸超过n +型区域的较深p +型区域。

10. 发明授权

US4727043A Method of manufacturing a non-volatile memory 失效
标题翻译：制造非易失性存储器的方法
公开(公告)号：US4727043A
公开(公告)日：1988-02-23
申请号：US792238
申请日：1985-10-29
申请人： Takashi Matsumoto , Motoo Nakano
发明人： Takashi Matsumoto , Motoo Nakano
IPC分类号： H01L21/8247 , H01L21/265 , H01L29/788 , H01L29/792 , H01L21/283
CPC分类号： H01L21/2652 , H01L29/7883
摘要： An improved electrically alterable read-only memory (EAROM) is offered by the method of the invention, the memory device comprising a floating gate type field effect transistor in which a part of the floating gate and a part of the drain region formed in a silicon substrate overlap. According to the method, impurity atoms are ion implanted into a part of a region where the drain region is to be formed through an insulation layer of silicon dioxide on the region. Thereafter, the insulation layer through which ion implantation was carried out is removed and a fresh insulation layer of silicon dioxide is formed where the old insulation layer was removed. By this method, a good, thin insulation film is fabricated. By virtue of the fresh insulation layer devoid of trap centers which trap electric charges, the insulation layer is free from defects that interrupt flow of electrons required for writing or erasing of information.
摘要翻译：通过本发明的方法提供改进的可电性可变的只读存储器（EAROM），该存储器件包括浮置栅型场效应晶体管，其中浮置栅极的一部分和漏极区的一部分形成于硅衬底重叠。根据该方法，通过该区域上的二氧化硅的绝缘层将杂质原子离子注入到要形成漏极区域的部分的一部分中。此后，去除进行离子注入的绝缘层，并且在旧绝缘层被去除的地方形成新的绝缘层二氧化硅。通过这种方法，制造出良好的薄绝缘膜。由于没有陷阱电荷的陷阱中心的新鲜绝缘层，绝缘层没有中断写入或擦除信息所需的电子流的缺陷。

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