专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08867271B2 Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device 有权
标题翻译：层叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
公开(公告)号：US08867271B2
公开(公告)日：2014-10-21
申请号：US13484088
申请日：2012-05-30
申请人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
发明人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠的非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

2. 发明申请

US20130279257A1 Erase Operation For 3D Non-Volatile Memory With Controllable Gate-Induced Drain Leakage Current 有权
公开(公告)号：US20130279257A1
公开(公告)日：2013-10-24
申请号：US13450313
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/04
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.

3. 发明授权

US08787094B2 Soft erase operation for 3D non-volatile memory with selective inhibiting of passed bits 有权
标题翻译：用于3D非易失性存储器的软擦除操作，选择性地禁止传递的位
公开(公告)号：US08787094B2
公开(公告)日：2014-07-22
申请号：US13450294
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C11/34 , G11C16/14 , G11C16/16 , G11C16/04
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障位。

4. 发明申请

US20130279256A1 Soft Erase Operation For 3D Non-Volatile Memory With Selective Inhibiting Of Passed Bits 有权
标题翻译：用于选择性禁止通过位的3D非易失性存储器的软擦除操作
公开(公告)号：US20130279256A1
公开(公告)日：2013-10-24
申请号：US13450294
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3445 , G11C5/02 , G11C11/5635 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/344 , G11C16/3472 , G11C29/52 , H01L27/11582 , H01L29/7926
摘要： An erase operation for a 3D stacked memory device selectively inhibits subsets of memory cells which meet a verify condition as the erase operation progresses. As a result, the faster-erasing memory cells are less likely to be over-erased and degradation is reduced. Each subset of memory cells can be independently erased by controlling a select gate, drain (SGD) transistor line, a bit line or a word line, according to the type of subset. For a SGD line subset or a bit line subset, the SGD line or bit line, respectively, is set at a level which inhibits erase. For a word line subset, the word line voltage is floated to inhibit erase. An inhibit or uninhibit status can be maintained for each subset, and each type of subset can have a different maximum allowable number of fail bits.
摘要翻译：对于3D堆叠存储器件的擦除操作，当擦除操作进行时，选择性地抑制满足验证条件的存储器单元的子集。结果，较快擦除的存储器单元不太可能被过度擦除并降低了降级。可以根据子集的类型，通过控制选择栅极，漏极（SGD）晶体管线，位线或字线来独立地擦除存储器单元的每个子集。对于SGD线子集或位线子集，SGD线或位线分别设置在抑制擦除的电平。对于字线子集，字线电压浮动以禁止擦除。可以为每个子集维持禁止或不禁止状态，并且每种类型的子集可以具有不同的最大允许数量的故障比特。

5. 发明授权

US09019775B2 Erase operation for 3D non-volatile memory with controllable gate-induced drain leakage current 有权
标题翻译：擦除具有可控制栅极漏极漏电流的3D非易失性存储器的操作
公开(公告)号：US09019775B2
公开(公告)日：2015-04-28
申请号：US13450313
申请日：2012-04-18
申请人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L Mui
发明人： Xiying Costa , Haibo Li , Masaaki Higashitani , Man L Mui
IPC分类号： G11C11/34 , G11C5/02 , G11C16/06 , H01L27/115 , G11C16/04 , G11C16/34
CPC分类号： G11C16/14 , G11C5/02 , G11C16/0483 , G11C16/06 , G11C16/3445 , G11C16/3472 , H01L27/1157 , H01L27/11582
摘要： An erase operation for a 3D stacked memory device applies an erase pulse which includes an intermediate level (Vgidl) and a peak level (Verase) to a set of memory cells, and steps up Vgidl in erase iterations of the erase operation. Vgidl can be stepped up when a specified portion of the cells have reached the erase verify level. In this case, a majority of the cells may have reached the erase verify level, such that the remaining cells can benefit from a higher gate-induced drain leakage (GIDL) current to reached the erase verify level. Verase can step up before and, optionally, after Vigdl is stepped up, but remain fixed while Vgidl is stepped. Vgidl can be stepped up until a maximum allowed level, Vgidl_max, is reached. Vgidl may be applied to a drain-side and/or source-side of a NAND string via a bit line or source line, respectively.
摘要翻译：用于3D堆叠存储器件的擦除操作将包括中间电平（Vgid1）和峰值电平（Verase）的擦除脉冲施加到一组存储器单元，并且在擦除操作的擦除迭代中对Vgid1进行升压。当指定部分的单元格已达到擦除验证级别时，可以升级Vgidl。在这种情况下，大多数单元可能已经达到擦除验证电平，使得剩余的单元可以从更高的栅极引起的漏极泄漏（GIDL）电流中受益，以达到擦除验证电平。 Verase可以在Vigdl加强之前，可选地升级，但在Vgidl步进时保持固定。 Vgidl可以升高直到达到最大允许电平Vgidl_max。 Vgid1可以分别经由位线或源极线施加到NAND串的漏极侧和/或源极侧。

6. 发明申请

US20130322174A1 Threshold Voltage Adjustment For A Select Gate Transistor In A Stacked Non-Volatile Memory Device 有权
标题翻译：用于堆叠非易失性存储器件中选择栅极晶体管的阈值电压调整
公开(公告)号：US20130322174A1
公开(公告)日：2013-12-05
申请号：US13484088
申请日：2012-05-30
申请人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
发明人： Haibo Li , Xiying Costa , Masaaki Higashitani , Man L. Mui
IPC分类号： G11C16/10
CPC分类号： G11C16/0483 , G11C29/025 , G11C29/028
摘要： In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
摘要翻译：在3D堆叠非易失性存储器件中，对串联存储器单元串的漏极端的选择栅极，漏极（SGD）晶体管评估和调整阈值电压。为了优化和紧固阈值电压分布，SGD晶体管在可接受范围的较低和较高电平下读取。具有低阈值电压的SGD晶体管进行编程，并且具有高阈值电压的SGD晶体管将被擦除，以使阈值电压达到可接受的范围。可以重复评估和调整，例如在相关子块的指定数量的编程擦除周期之后。重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。方面包括通过验证和抑制来编程SGD晶体管，擦除具有验证和抑制的SGD晶体管，以及上述两者。

7. 发明授权

US08488382B1 Erase inhibit for 3D non-volatile memory 有权
标题翻译：擦除3D非易失性存储器的禁止
公开(公告)号：US08488382B1
公开(公告)日：2013-07-16
申请号：US13332868
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa
发明人： Haibo Li , Xiying Costa
IPC分类号： G11C11/34
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/344
摘要： An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced.
摘要翻译：用于3D堆叠存储器件的擦除处理执行NAND串的双面擦除，直到多个NAND串中的一个通过擦除验证测试，然后执行剩余NAND串的单面擦除。双面擦除从源极侧和漏极侧端部充电NAND串的本体，而单面擦除从漏极侧端部充电NAND串的本体。与一个位线相关联的NAND串形成一组。当设置满足设置的擦除验证条件（例如通过擦除验证测试的组的NAND串的一个，全部或某些指定部分）时，可能会切换到单面擦除。当不超过指定数量的NAND串未达到擦除验证测试时，擦除操作可以结束。结果，减少了存储单元的擦除劣化。

8. 发明申请

US20130163336A1 Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory 有权
标题翻译：通过控制选择栅极电压擦除操作，用于3D非易失性存储器
公开(公告)号：US20130163336A1
公开(公告)日：2013-06-27
申请号：US13332844
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa , Chenfeng Zhang
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/04
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
摘要翻译：用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极（SGD）和源极选择栅极（SGS）。在一种方法中，驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压，同时将擦除电压施加到位线或源极线。可以产生在选择栅极处更一致的栅极引起的漏极漏极（GIDL），以对NAND串的体进行充电。此外，可以用擦除电压来升高选择栅极电压，以避免导致退化的选择栅极之间的过多的漏极 - 栅极电压。选择栅极电压的升高可以从擦除操作的第一次擦除验证迭代开始，或者以预定或自适应确定的擦除验证迭代（例如基于编程擦除周期的数量）开始。

9. 发明授权

US08908435B2 Erase operation with controlled select gate voltage for 3D non-volatile memory 有权
公开(公告)号：US08908435B2
公开(公告)日：2014-12-09
申请号：US13332844
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa , Chenfeng Zhang
发明人： Haibo Li , Xiying Costa , Chenfeng Zhang
IPC分类号： G11C16/16
CPC分类号： G11C16/16 , G11C16/0483 , G11C16/344
摘要： An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.

10. 发明申请

US20130163337A1 Erase Inhibit For 3D Non-Volatile Memory 有权
公开(公告)号：US20130163337A1
公开(公告)日：2013-06-27
申请号：US13332868
申请日：2011-12-21
申请人： Haibo Li , Xiying Costa
发明人： Haibo Li , Xiying Costa
IPC分类号： G11C16/16 , G11C16/04
CPC分类号： G11C16/04 , G11C16/0483 , G11C16/16 , G11C16/3418 , G11C16/344
摘要： An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式