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    • 1. 发明授权
    • Threshold voltage adjustment for a select gate transistor in a stacked non-volatile memory device
    • 层叠非易失性存储器件中的选择栅极晶体管的阈值电压调整
    • US08867271B2
    • 2014-10-21
    • US13484088
    • 2012-05-30
    • Haibo LiXiying CostaMasaaki HigashitaniMan L. Mui
    • Haibo LiXiying CostaMasaaki HigashitaniMan L. Mui
    • G11C11/34
    • G11C16/0483G11C29/025G11C29/028
    • In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
    • 在3D堆叠的非易失性存储器件中,对串联存储器单元串的漏极端的选择栅极,漏极(SGD)晶体管评估和调整阈值电压。 为了优化和紧固阈值电压分布,SGD晶体管在可接受范围的较低和较高电平下读取。 具有低阈值电压的SGD晶体管进行编程,并且具有高阈值电压的SGD晶体管将被擦除,以使阈值电压达到可接受的范围。 可以重复评估和调整,例如在相关子块的指定数量的编程擦除周期之后。 重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。 方面包括通过验证和抑制来编程SGD晶体管,擦除具有验证和抑制的SGD晶体管,以及上述两者。
    • 6. 发明申请
    • Threshold Voltage Adjustment For A Select Gate Transistor In A Stacked Non-Volatile Memory Device
    • 用于堆叠非易失性存储器件中选择栅极晶体管的阈值电压调整
    • US20130322174A1
    • 2013-12-05
    • US13484088
    • 2012-05-30
    • Haibo LiXiying CostaMasaaki HigashitaniMan L. Mui
    • Haibo LiXiying CostaMasaaki HigashitaniMan L. Mui
    • G11C16/10
    • G11C16/0483G11C29/025G11C29/028
    • In a 3D stacked non-volatile memory device, the threshold voltages are evaluated and adjusted for select gate, drain (SGD) transistors at drain ends of strings of series-connected memory cells. To optimize and tighten the threshold voltage distribution, the SGD transistors are read at lower and upper levels of an acceptable range. SGD transistors having a low threshold voltage are subject to programming, and SGD transistors having a high threshold voltage are subject to erasing, to bring the threshold voltage into the acceptable range. The evaluation and adjustment can be repeated such as after a specified number of program-erase cycles of an associated sub-block. The condition for repeating the evaluation and adjustment can be customized for different groups of SGD transistors. Aspects include programming SGD transistors with verify and inhibit, erasing SGD transistors with verify and inhibit, and both of the above.
    • 在3D堆叠非易失性存储器件中,对串联存储器单元串的漏极端的选择栅极,漏极(SGD)晶体管评估和调整阈值电压。 为了优化和紧固阈值电压分布,SGD晶体管在可接受范围的较低和较高电平下读取。 具有低阈值电压的SGD晶体管进行编程,并且具有高阈值电压的SGD晶体管将被擦除,以使阈值电压达到可接受的范围。 可以重复评估和调整,例如在相关子块的指定数量的编程擦除周期之后。 重复评估和调整的条件可以针对不同的SGD晶体管组进行定制。 方面包括通过验证和抑制来编程SGD晶体管,擦除具有验证和抑制的SGD晶体管,以及上述两者。
    • 7. 发明授权
    • Erase inhibit for 3D non-volatile memory
    • 擦除3D非易失性存储器的禁止
    • US08488382B1
    • 2013-07-16
    • US13332868
    • 2011-12-21
    • Haibo LiXiying Costa
    • Haibo LiXiying Costa
    • G11C11/34
    • G11C16/04G11C16/0483G11C16/16G11C16/3418G11C16/344
    • An erase process for a 3D stacked memory device performs a two-sided erase of NAND strings until one of more of the NAND strings passes an erase-verify test, then a one-sided erase of the remaining NAND strings is performed. The two-sided erase charges up the body of a NAND string from the source-side and drain-side ends, while the one-sided erase charges up the body of the NAND string from the drain-side end. The NAND strings associated with one bit line form a set. The switch to the one-sided erase can occur when the set meets a set erase-verify condition, such as one, all, or some specified portion of the NAND strings of the set passing the erase-verify test. The erase operation can end when no more than a specified number of NAND strings have not met the erase-verify test. As a result, erase degradation of the memory cells is reduced.
    • 用于3D堆叠存储器件的擦除处理执行NAND串的双面擦除,直到多个NAND串中的一个通过擦除验证测试,然后执行剩余NAND串的单面擦除。 双面擦除从源极侧和漏极侧端部充电NAND串的本体,而单面擦除从漏极侧端部充电NAND串的本体。 与一个位线相关联的NAND串形成一组。 当设置满足设置的擦除验证条件(例如通过擦除验证测试的组的NAND串的一个,全部或某些指定部分)时,可能会切换到单面擦除。 当不超过指定数量的NAND串未达到擦除验证测试时,擦除操作可以结束。 结果,减少了存储单元的擦除劣化。
    • 8. 发明申请
    • Erase Operation With Controlled Select Gate Voltage For 3D Non-Volatile Memory
    • 通过控制选择栅极电压擦除操作,用于3D非易失性存储器
    • US20130163336A1
    • 2013-06-27
    • US13332844
    • 2011-12-21
    • Haibo LiXiying CostaChenfeng Zhang
    • Haibo LiXiying CostaChenfeng Zhang
    • G11C16/04
    • G11C16/16G11C16/0483G11C16/344
    • An erase process for a 3D stacked memory device controls a drain-side select gate (SGD) and a source-side select gate (SGS) of a NAND string. In one approach, SGD and SGS are driven to provide a predictable drain-to-gate voltage across the select gates while an erase voltage is applied to a bit line or source line. A more consistent gate-induced drain leakage (GIDL) at the select gates can be generated to charge up the body of the NAND string. Further, the select gate voltage can be stepped up with the erase voltage to avoid an excessive drain-to-gate voltage across the select gates which causes degradation. The step up in the select gate voltage can begin with the first erase-verify iteration of an erase operation, or at a predetermined or adaptively determined erase-verify iteration, such as based on a number of program-erase cycles.
    • 用于3D堆叠存储器件的擦除处理控制NAND串的漏极侧选择栅极(SGD)和源极选择栅极(SGS)。 在一种方法中,驱动SGD和SGS以在选择栅极上提供可预测的漏极到栅极电压,同时将擦除电压施加到位线或源极线。 可以产生在选择栅极处更一致的栅极引起的漏极漏极(GIDL),以对NAND串的体进行充电。 此外,可以用擦除电压来升高选择栅极电压,以避免导致退化的选择栅极之间的过多的漏极 - 栅极电压。 选择栅极电压的升高可以从擦除操作的第一次擦除验证迭代开始,或者以预定或自适应确定的擦除验证迭代(例如基于编程擦除周期的数量)开始。