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1. 发明授权

US07894267B2 Deterministic programming algorithm that provides tighter cell distributions with a reduced number of programming pulses 有权
标题翻译：确定性编程算法，提供更小的单元分布，减少编程脉冲数
公开(公告)号：US07894267B2
公开(公告)日：2011-02-22
申请号：US11929741
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C11/34 , G11C16/04
CPC分类号： G11C16/10 , G11C16/12
摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.
摘要翻译：改进存储器件编程的系统和方法。脉冲分量将不同的编程脉冲施加到存储单元。分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及脉冲分量将一个或多个编程脉冲施加到存储器单元。

2. 发明申请

US20090109758A1 NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE 有权
标题翻译：非易失性存储器阵列分区结构和使用单层电池和多级电池在方法中的方法
公开(公告)号：US20090109758A1
公开(公告)日：2009-04-30
申请号：US11929761
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C16/0491
摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.
摘要翻译：一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。

3. 发明申请

US20090109760A1 DETERMINISTIC PROGRAMMING ALGORITHM THAT PROVIDES TIGHTER CELL DISTRIBUTIONS WITH A REDUCED NUMBER OF PROGRAMMING PULSES 有权
标题翻译：提供具有减少编程脉冲数的加密单元分配的确定性编程算法
公开(公告)号：US20090109760A1
公开(公告)日：2009-04-30
申请号：US11929741
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/12
摘要： Systems and methods for improving the programming of memory devices. A pulse component applies different programming pulses to a memory cell. An analysis component measures values of one or more characteristics of the memory cell as a function of the applied different programming pulses. A computation component computes the applied different programming pulses as a function of the measured values of the one or more characteristics of the memory cell. The analysis component measures one or more values of the one or more characteristics of the memory cell, the computation component computes one or more programming pulses as a function of the one or more measured values of the one or more characteristics of the memory cell, and the pulse component applies the one or more programming pulses to the memory cell.
摘要翻译：改进存储器件编程的系统和方法。脉冲分量将不同的编程脉冲施加到存储单元。分析组件根据应用的不同编程脉冲测量存储器单元的一个或多个特性的值。计算组件根据存储单元的一个或多个特性的测量值来计算应用的不同编程脉冲。分析组件测量存储器单元的一个或多个特性的一个或多个值，计算组件根据存储器单元的一个或多个特性的一个或多个测量值来计算一个或多个编程脉冲，以及脉冲分量将一个或多个编程脉冲施加到存储器单元。

4. 发明申请

US20090109721A1 NONVOLATILE MEMORY ARRAY PARTITIONING ARCHITECTURE AND METHOD TO UTILIZE SINGLE LEVEL CELLS AND MULTI LEVEL CELLS WITHIN SAID ARCHITECTURE. 有权
标题翻译：非易失性存储器阵列分区结构和方法，用于在单一结构中利用单层电池和多级电池。
公开(公告)号：US20090109721A1
公开(公告)日：2009-04-30
申请号：US11929724
申请日：2007-10-30
申请人： Hagop Nazarian , Harry Kuo , Michael Achter
发明人： Hagop Nazarian , Harry Kuo , Michael Achter
IPC分类号： G11C5/06
CPC分类号： G11C8/14 , G11C8/08 , G11C16/0416 , G11C16/0491 , G11C16/10
摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.
摘要翻译：一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。多对NVM单元电连接到字线和位线。每对NVM单元包括第一存储单元和第二存储单元。第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。第一存储单元的第一源极/漏极连接到位线之一。第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。第二存储单元的第二源极/漏极连接到另一个位线。第一和第二存储单元的控制栅极连接到不同的字线。

5. 发明授权

US07567457B2 Nonvolatile memory array architecture 有权
标题翻译：非易失性存储器阵列架构
公开(公告)号：US07567457B2
公开(公告)日：2009-07-28
申请号：US11929724
申请日：2007-10-30
申请人： Hagop Nazarian , Harry Kuo , Michael Achter
发明人： Hagop Nazarian , Harry Kuo , Michael Achter
IPC分类号： G11C11/34 , G11C16/04 , G11C5/06
CPC分类号： G11C8/14 , G11C8/08 , G11C16/0416 , G11C16/0491 , G11C16/10
摘要： An apparatus comprising a two or three dimensional array of a plurality of pairs of non-volatile memory (“NVM”) cells coupled to enable program and erase of the NVM cells. The plurality of pairs of NVM cells is electrically connected to word lines and bit lines. Each pair of NVM cells comprises a first memory cell and a second memory cell. The first and second memory cells comprise a first source/drain, a second source/drain, and a control gate. The first source/drain of the first memory cell is connected to one of the bit lines. The second source/drain of the first memory cell is connected to the first source/drain of the second memory cell. The second source/drain of the second memory cell is connected to another one of the bit lines. The control gates of the first and second memory cells are connected to different word lines.
摘要翻译：一种包括多对非易失性存储器（“NVM”）单元的二维或三维阵列的装置，其被耦合以使能NVM单元的编程和擦除。多对NVM单元电连接到字线和位线。每对NVM单元包括第一存储单元和第二存储单元。第一和第二存储单元包括第一源极/漏极，第二源极/漏极和控制栅极。第一存储单元的第一源极/漏极连接到位线之一。第一存储单元的第二源极/漏极连接到第二存储单元的第一源极/漏极。第二存储单元的第二源极/漏极连接到另一个位线。第一和第二存储单元的控制栅极连接到不同的字线。

6. 发明授权

US07995385B2 Memory array of pairs of nonvolatile memory cells using Fowler-Nordheim programming and erasing 有权
标题翻译：使用Fowler-Nordheim编程和擦除的非易失性存储器单元对的存储器阵列
公开(公告)号：US07995385B2
公开(公告)日：2011-08-09
申请号：US11929761
申请日：2007-10-30
申请人： Hagop Nazarian , Michael Achter , Harry Kuo
发明人： Hagop Nazarian , Michael Achter , Harry Kuo
IPC分类号： G11C16/06
CPC分类号： G11C16/0416 , G11C16/0491
摘要： A system comprising a program component that programs one or more non-volatile memory (“NVM”) cells of an array of pairs of NVM cells using FN tunneling, an erase component that erases the one or more NVM cells of the array of pairs of NVM cells using FN tunneling, and a read component that reads the one or more NVM cells of the array of pairs of NVM cells.
摘要翻译：一种包括程序组件的系统，该程序组件使用FN隧道对一组或多个NVM单元阵列的一个或多个非易失性存储器（“NVM”）单元进行编程，所述擦除组件擦除所述NVM单元阵列的一对或多个NVM单元使用FN隧道的NVM单元，以及读取组件，其读取NVM单元阵列阵列中的一个或多个NVM单元。

7. 发明授权

US07835189B2 High accuracy adaptive programming 有权
标题翻译：高精度自适应编程
公开(公告)号：US07835189B2
公开(公告)日：2010-11-16
申请号：US11687492
申请日：2007-03-16
申请人： Michael Achter , Hagop Nazarian
发明人： Michael Achter , Hagop Nazarian
IPC分类号： G11C16/06
CPC分类号： G11C16/10
摘要： Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.
摘要翻译：闪存设备具有可被擦除和编程的多个存储器单元。执行电压验证检查允许将适当的状态变化电压施加到闪存器件。通过访问查找表来确定适当的状态变化电压。使用适当的状态变化电压允许电池在更多的总体编程周期下运行。

8. 发明申请

US20080225596A1 HIGH ACCURACY ADAPTIVE PROGRAMMING 有权
标题翻译：高精度自适应编程
公开(公告)号：US20080225596A1
公开(公告)日：2008-09-18
申请号：US11687492
申请日：2007-03-16
申请人： Michael Achter , Hagop Nazarian
发明人： Michael Achter , Hagop Nazarian
IPC分类号： G11C7/00
CPC分类号： G11C16/10
摘要： Flash memory devices have a plurality of memory cells that can be erased and programmed. Performing a voltage verification check allows a for an appropriate state-change voltage to be applied to the flash memory device. The appropriate state-change voltage is determined though accessing a look-up table. Using an appropriate state-change voltage allows a cell to operate with more overall programming cycles.
摘要翻译：闪存设备具有可被擦除和编程的多个存储器单元。执行电压验证检查允许将适当的状态变化电压施加到闪存器件。通过访问查找表来确定适当的状态变化电压。使用适当的状态变化电压允许电池在更多的总体编程周期下运行。

9. 发明授权

US07558101B1 Scan sensing method that improves sensing margins 有权
标题翻译：扫描感测方法，可提高感光度
公开(公告)号：US07558101B1
公开(公告)日：2009-07-07
申请号：US11957366
申请日：2007-12-14
申请人： Hagop Nazarian , Michael Achter
发明人： Hagop Nazarian , Michael Achter
IPC分类号： G11C11/00 , G11C11/15 , G11C11/34
CPC分类号： G11C7/06 , G11C7/08 , G11C16/26 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/50
摘要： Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli.
摘要翻译：通过利用最佳参考刺激来改善记忆细胞感受边缘的系统和方法。刺激分量将多个不同的参考刺激应用于存储器件的多个存储单元。感测组件根据串行应用的多个不同的参考刺激来感测多个存储器单元中的每个存储器单元的特性。分析组件通过选择多个不同参考刺激中的一个来计算最佳参考刺激，所述多个不同参考刺激中的一个与根据应用的多个参考刺激的函数改变状态的存储器单元特性的绝对最小值的绝对最小值相关联不同的参考刺激。

10. 发明申请

US20090154260A1 SCAN SENSING METHOD THAT IMPROVES SENSING MARGINS 有权
标题翻译：扫描感测方法改善感光度
公开(公告)号：US20090154260A1
公开(公告)日：2009-06-18
申请号：US11957366
申请日：2007-12-14
申请人： Hagop Nazarian , Michael Achter
发明人： Hagop Nazarian , Michael Achter
IPC分类号： G11C7/00
CPC分类号： G11C7/06 , G11C7/08 , G11C16/26 , G11C29/02 , G11C29/026 , G11C29/028 , G11C29/50
摘要： Systems and methods for improving memory cell sensing margins by utilizing an optimal reference stimulus. A stimulus component applies a plurality of different reference stimuli to a plurality of memory cells of a memory device. A sense component senses a characteristic of each memory cell of the plurality of memory cells as a function of the serially applied plurality of different reference stimuli. An analysis component computes an optimal reference stimulus by selecting one of the plurality of different reference stimuli, the one of the plurality of different reference stimuli associated with an absolute minima of number of memory cell characteristics that changed state as a function of the applied plurality of different reference stimuli
摘要翻译：通过利用最佳参考刺激来改善记忆细胞感受边缘的系统和方法。刺激分量将多个不同的参考刺激应用于存储器件的多个存储单元。感测组件根据串行应用的多个不同的参考刺激来感测多个存储器单元中的每个存储器单元的特性。分析组件通过选择多个不同参考刺激中的一个来计算最佳参考刺激，所述多个不同参考刺激中的一个与根据应用的多个参考刺激的函数改变状态的存储器单元特性的绝对最小值的绝对最小值相关联不同的参考刺激

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