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    • 2. 发明申请
    • Carry look-ahead adder having a reduced area
    • 携带前进加法器具有减小的面积
    • US20050091299A1
    • 2005-04-28
    • US10740444
    • 2003-12-22
    • Haeng KoKyoung JhangOh Kwon
    • Haeng KoKyoung JhangOh Kwon
    • G06F7/50G06F7/508
    • G06F7/508
    • The present invention relates to a carry look-ahead adder. The carry look-ahead adder is configured in 4-bit units in general. Each 4-bt carry look-ahead adder is combined with a carry look-ahead generating unit to constitute a carry look-ahead adder that can process input signals of larger size. The carry look-ahead adder according to the embodiment of the present invention calculates carry of each bit sequentially not by using any carry generation function or any carry propagation function but by using previous bit when generating an internal carry in the adder, so that propagation delay is allowed a little but the logic gate circuit can be simplified.
    • 本发明涉及进位查询加法器。 一般来说,进位前视加法器以4位为单位进行配置。 每个4-bt进位预读加法器与进位预读生成单元相结合,构成可处理较大尺寸的输入信号的进位先行加法器。 根据本发明的实施例的进位预读加法器按照不是使用任何进位产生函数或任何进位传播函数顺序地计算每个比特的进位,而是在加法器中产生内部进位时使用先前的比特,从而传播延迟 允许一点,但可以简化逻辑门电路。