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1. 发明专利

DE10332590B4 Zeilendecodierer in einem Flashspeicher sowie Löschverfahren für eine Flashspeiicherzelle in diesem 未知
公开(公告)号：DE10332590B4
公开(公告)日：2011-12-08
申请号：DE10332590
申请日：2003-07-17
申请人： HYNIX SEMICONDUCTOR INC
发明人： KIM KI SEOG , LEE KEUN WOO , PARK SUNG KEE , JEON YOO NAM
IPC分类号： G11C16/06 , G11C16/14 , G11C16/02 , G11C16/08 , G11C16/16 , G11C29/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： Zeilendecodierer in einem Flashspeicher, mit: – einem PMOS-Transistor mit einer Gateelektrode zum Empfangen eines ersten Eingangssignals als Eingangssignal, der zwischen einen ersten Versorgungsspannungsanschluss und einen ersten Knoten geschaltet ist; – einem ersten NMOS-Transistor mit einer Gateelektrode zum Empfangen des ersten Eingangssignals als Eingangssignal, der zwischen den ersten Knoten und einen zweiten Knoten geschaltet ist; – einem zweiten NMOS-Transistor mit einer Gateelektrode zum Empfangen des zweiten Eingangssignals als Eingangssignal, der zwischen den zweiten Knoten und einen Masseanschluss geschaltet ist; und – einer Schalteinrichtung mit einer Gateelektrode zum Empfangen des dritten Eingangssignals als Eingangssignal, der zwischen den zweiten Knoten und einen zweiten Versorgungsspannungsanschluss geschaltet ist; – wobei der erste Knoten mit Wortleitungen verbunden ist.

2. 发明专利

DE10332590A1 未知
公开(公告)号：DE10332590A1
公开(公告)日：2004-03-25
申请号：DE10332590
申请日：2003-07-17
申请人： HYNIX SEMICONDUCTOR INC
发明人： KIM KI SEOG , LEE KEUN WOO , PARK SUNG KEE , JEON YOO NAM
IPC分类号： G11C16/06 , G11C16/02 , G11C16/08 , G11C16/14 , G11C16/16 , G11C29/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
摘要： A row decoder in a flash memory comprises a first switch to selectively couple a word line to a first voltage terminal, and a second switch to selectively couple the word line to a second voltage terminal. The row decoder also comprises a third switch to selectively couple the word line to a third voltage terminal.

3. 发明专利

DE10164298A1 未知
公开(公告)号：DE10164298A1
公开(公告)日：2003-06-05
申请号：DE10164298
申请日：2001-12-28
申请人： HYNIX SEMICONDUCTOR INC
发明人： KIM KI SEOG , YOU YOUNG SEON , LEE KEUN WOO , PARK SUNG KEE
IPC分类号： G01R27/02 , H01L21/3205 , H01L21/66 , H01L21/822 , H01L23/52 , H01L23/544 , H01L27/04
摘要： The present invention relates to a test pattern for measuring a contact resistance and method of manufacturing the same. In order to confirm that a contact resistance suitable for a semiconductor device before an actual process for manufacturing the device is performed, the present invention designs a test pattern for measuring the contact resistance depending on a design rule of a line contact actually applied to an actual device. At this time, a first line contact region and a second line contact region are formed between a word line so that a line contact region can form a pair; a plurality of sources are formed in the first line contact region and a plurality of sources are formed in the second line contact region wherein neighboring sources are connected by diffusion layers so that the first line contact region and the second line contact region can be electrically connected; and a plurality of line contact patterns are formed so that the plurality of the sources can be electrically connected by every two in each of the first and second line contact regions wherein the line contact pattern formed in the first line contact region and the line contact pattern formed in the second line contact region are alternately positioned. Therefore, the present invention can allow current for measuring the resistance sequentially along the first line contact region and the second line contact region to measure the line contact resistance in which the contact resistance in every source portion is considered.

4. 发明专利

JP2004055134A Row decoder of flash memory and erasing method of flash memory using the row decoder 审中-公开
标题翻译：闪存解码器的ROW解码器和使用ROW解码器的闪存存储器的擦除方法
公开(公告)号：JP2004055134A
公开(公告)日：2004-02-19
申请号：JP2003274800
申请日：2003-07-15
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： KIM KI SEOG , LEE KEUN WOO , BOKU NARIMOTO , JEON YOO NAM
IPC分类号： G11C16/06 , G11C16/02 , G11C16/08 , G11C16/14 , G11C16/16 , G11C29/00 , H01L21/8247 , H01L27/10 , H01L27/115 , H01L29/788 , H01L29/792
CPC分类号： G11C16/08 , G11C16/16 , G11C29/70
摘要： PROBLEM TO BE SOLVED: To provide a row decoder of a flash memory that can prevent a breakdown phenomenon in an ONO insulating film occurring in erasing operation in an E/W cycle test or the like, and to provide an erasing method of the flash memory using the row decoder. SOLUTION: The row decoder includes a PMOS transistor that receives a first input signal in a gate electrode and is connected between a first power supply terminal an a first node; a first NMOS transistor that receives the first input signal at the gate electrode and is connected between the first and second nodes; a second NMOS transistor that receives a second input signal at the gate electrode and is connected between the second node and an earth terminal; and a switch means that receives a third input signal in the gate electrode and is connected between the second node and a second power supply terminal. In this case, the first node is connected to the word line of a memory matrix. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种闪存的行解码器，其可以防止在E / W循环测试等中的擦除操作中发生的ONO绝缘膜中的击穿现象，并且提供擦除方法闪存使用行解码器。解决方案：行解码器包括：PMOS晶体管，其接收栅极电极中的第一输入信号，并连接在第一电源端子和第一节点之间; 第一NMOS晶体管，其在栅电极处接收第一输入信号，并且连接在第一和第二节点之间; 第二NMOS晶体管，其在所述栅电极处接收第二输入信号，并且连接在所述第二节点和接地端子之间; 以及开关装置，其接收所述栅电极中的第三输入信号，并且连接在所述第二节点和第二电源端子之间。在这种情况下，第一节点连接到存储器矩阵的字线。版权所有（C）2004，JPO

5. 发明专利

JP2005025917A Readout method for flash memory 审中-公开
标题翻译：闪存存储器的读出方法
公开(公告)号：JP2005025917A
公开(公告)日：2005-01-27
申请号：JP2004070358
申请日：2004-03-12
申请人： Hynix Semiconductor Inc , 株式会社ハイニックスセミコンダクター
发明人： KIM KI SEOG
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06 , G11C16/26 , G11C16/28
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/28
摘要： PROBLEM TO BE SOLVED: To improve resolution ability of a readout operation, shorten the time required for discrimination and reduce the size of a transistor constituting a memory cell and an information discriminating device, by changing the form of a voltage applied in the readout operation of a flash memory. SOLUTION: In the readout method of a flash memory cell which includes a gate terminal, a drain terminal and a source terminal, a channel voltage is applied to the gate terminal, which is lower than a threshold voltage, in a state in which the memory cell is programmed and higher than a threshold voltage in a state in which the memory cell is erased. To the drain terminal a readout voltage is applied, which is lower than the source voltage and higher than the ground voltage, and to the source terminal the source voltage is applied. Information stored in the memory cell is read out, by comparing the variation of the reading voltage of the drain terminal with a read reference voltage. COPYRIGHT: (C)2005,JPO&NCIPI
摘要翻译：要解决的问题：为了提高读出操作的分辨能力，通过改变施加在存储单元中的电压的形式来缩短鉴别所需的时间并减小构成存储单元的晶体管和信息鉴别装置的尺寸闪存的读出操作。解决方案：在包括栅极端子，漏极端子和源极端子的闪存单元的读出方法中，在低于阈值电压的栅极端子上施加沟道电压，处于其中存储器单元被编程并且高于在存储单元被擦除的状态下的阈值电压。向漏极端子施加低于源极电压并高于接地电压的读出电压，并向源极端子施加源极电压。通过比较漏极端子的读取电压与读取的参考电压的变化来读出存储在存储单元中的信息。版权所有（C）2005，JPO＆NCIPI

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