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1. 发明申请

WO2015032358A1 SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH ASYNCHRONOUS INSTRUCTION FETCH, DECODE, AND ISSUE 审中-公开
标题翻译：具有异步指令的异步处理器的系统和方法，解码和发布
公开(公告)号：WO2015032358A1
公开(公告)日：2015-03-12
申请号：PCT/CN2014/086115
申请日：2014-09-09
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： GE, Yiqun , SHI, Wuxian , ZHANG, Qifan , HUANG, Tao , TONG, Wen
IPC分类号： H04L29/06
CPC分类号： G06F9/38 , G06F9/3802 , G06F9/3836 , G06F9/3869 , G06F9/3871
摘要： Embodiments are provided for an asynchronous processor with an asynchronous Instruction fetch, decode, and issue unit. The asynchronous processor comprises an execution unit for asynchronous execution of a plurality of instructions, and a fetch, decode and issue unit configured for asynchronous decoding of the instructions. The fetch, decode and issue unit comprises a plurality of resources supporting functions of the fetch, decode and issue unit, and a plurality of decoders arranged in a predefined order for passing a plurality of tokens. The tokens control access of the decoders to the resources and allow the decoders exclusive access to the resources. The fetch, decode and issue unit also comprises an issuer unit for issuing the instructions from the decoders to the execution unit
摘要翻译：为具有异步指令提取，解码和发布单元的异步处理器提供实施例。异步处理器包括用于异步执行多个指令的执行单元，以及被配置用于对指令进行异步解码的读取，解码和发布单元。获取，解码和发布单元包括支持获取，解码和发布单元的功能的多个资源，以及以预定顺序排列以传送多个令牌的多个解码器。令牌控制解码器对资源的访问，并允许解码器独占访问资源。提取，解码和发布单元还包括用于从解码器向执行单元发出指令的发行者单元

2. 发明申请

WO2018050063A1 METHOD AND APPARATUS FOR ENCODING DATA USING A POLAR CODE 审中-公开
标题翻译：使用极坐标编码来编码数据的方法和设备
公开(公告)号：WO2018050063A1
公开(公告)日：2018-03-22
申请号：PCT/CN2017/101531
申请日：2017-09-13
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： ZHANG, Huazi , TONG, Jiajie , LI, Rong , WANG, Jun , TONG, Wen , GE, Yiqun , LIU, Xiaocheng , ZHANG, Gongzheng , WANG, Jian , CHENG, Nan , ZHANG, Qifan
IPC分类号： H03M13/09
摘要： Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of "ones" in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of "ones" in the binary representation of the sub-channel index (further described below). In one embodiment， candidate sub-channels that have certain row weight values are reserved for parity bit (s). Thereafter, K information bits may be mapped to the K most reliable remaining sub-channels, and a number of frozen bits (e.g. N-K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels, and parity bit values are determined based on a function of the information bits.
摘要翻译：实施例技术基于其行权重将奇偶位映射到子信道。子频道的行权重可以被视为“1”的数量。在Kronecker矩阵的相应行中，或者作为指数（即汉明重量）为“1”的数目的2的幂。在子信道索引的二进制表示中（下面进一步描述）。在一个实施例中，具有特定行权值的候选子信道被保留用于奇偶校验位。此后，可以将K个信息比特映射到K个最可靠的剩余子信道，并且可以将多个冻结比特（例如N-K）映射到最不可靠的剩余子信道。奇偶比特然后可以映射到候选子信道，并且基于信息比特的函数来确定奇偶比特值。

3. 发明申请

WO2015035330A1 METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR REMOVAL OF META-STABILITY 审中-公开
标题翻译：用于异相处理器去除元稳定性的方法和装置
公开(公告)号：WO2015035330A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054610
申请日：2014-09-08
申请人： FUTUREWEI TECHNOLOGIES, INC. , HUAWEI TECHNOLOGIES CO., LTD.
发明人： HUANG, Tao , ZHANG, Qifan , SHI, Wuxian , GE, Yiqun , TONG, Wen
IPC分类号： G06F9/44
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system having a plurality of pipelined processing stages utilizes self-clocked generators to tune the delay needed in each of the processing stages to complete the processing cycle. Because different processing stages may require different amounts of time to complete processing or may require different delays depending on the processing required in a particular stage, the self-clocked generators may be tuned to each stage's necessary delay(s) or may be programmably configured.
摘要翻译：具有多个流水线处理级的无时钟异步处理电路或系统利用自定时发生器来调整每个处理阶段所需的延迟以完成处理周期。因为不同的处理阶段可能需要不同的时间量来完成处理，或者可能需要根据特定阶段中所需的处理而产生不同的延迟，所以自定时发生器可以被调谐到每个阶段的必要延迟或者可被编程地配置。

4. 发明申请

WO2018050062A1 METHOD AND APPARATUS FOR ENCODING DATA USING A POLAR CODE 审中-公开
标题翻译：使用极坐标编码来编码数据的方法和设备
公开(公告)号：WO2018050062A1
公开(公告)日：2018-03-22
申请号：PCT/CN2017/101528
申请日：2017-09-13
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： ZHANG, Huazi , TONG, Jiajie , LI, Rong , WANG, Jun , TONG, Wen , GE, Yiqun , LIU, Xiaocheng , ZHANG, Gongzheng , WANG, Jian , CHENG, Nan , ZHANG, Qifan
IPC分类号： H03M13/13
摘要： Embodiment techniques map parity bits to sub-channels based on their row weights. The row weight for a sub-channel may be viewed as the number of "ones" in the corresponding row of the Kronecker matrix or as a power of 2 with the exponent (i.e. the hamming weight) being the number of "ones" in the binary representation of the sub-channel index (further described below). In one embodiment， candidate sub-channels that have certain row weight values are reserved for parity bit (s). Thereafter， K information bits may be mapped to the K most reliable remaining sub-channels， and a number of frozen bits (e.g. N-K) may be mapped to the least reliable remaining sub-channels. Parity bits may then mapped to the candidate sub-channels， and parity bit values are determined based on a function of the information bits.
摘要翻译：实施例技术基于其行权重将奇偶位映射到子信道。子频道的行权重可以被视为“1”的数量。在Kronecker矩阵的相应行中，或者作为指数（即汉明重量）为“1”的数目的2的幂。在子信道索引的二进制表示中（下面进一步描述）。在一个实施例中，具有特定行权值的候选子信道被保留用于奇偶校验位。此后，可以将K个信息比特映射到K个最可靠的剩余子信道，并且可以将多个冻结比特（例如N-K）映射到最不可靠的剩余子信道。奇偶比特然后可以映射到候选子信道，并且基于信息比特的函数来确定奇偶比特值。

5. 发明申请

WO2015035339A1 SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH HETEROGENEOUS PROCESSORS 审中-公开
标题翻译：具有异质处理器的异步加工器的系统和方法
公开(公告)号：WO2015035339A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054619
申请日：2014-09-08
申请人： HUAWEI TECHNOLOGIES CO., LTD. , FUTUREWEI TECHNOLOGIES, INC.
发明人： GE, Yiqun , SHI, Wuxian , ZHANG, Qifan , HUANG, Tao , TONG, Wen
IPC分类号： G06F15/16
CPC分类号： G06F9/3836 , G06F9/3001 , G06F9/30145 , G06F9/3838 , G06F9/3871
摘要： Embodiments are provided for an asynchronous processor with heterogeneous processors. In an embodiment, the apparatus for an asynchronous processor comprises a memory configured to cache instructions, and a first unit (XU) configured to processing a first instruction of the instructions. The apparatus also comprises a second XU having less restricted access than the first XU to a resource of the asynchronous processor and configured to process a second instruction of the instructions. The second instruction has higher priority or requires faster access to the resource than the first instruction. The apparatus further comprises a feedback engine configured to decode the first instruction and the second instruction, and issue the first instruction to the first XU, and a scheduler configured to send the second instruction to the second XU.
摘要翻译：为具有异构处理器的异步处理器提供实施例。在一个实施例中，用于异步处理器的装置包括被配置为缓存指令的存储器以及被配置为处理指令的第一指令的第一单元（XU）。所述装置还包括第二XU，其具有比所述第一XU更少受限于所述异步处理器的资源的访问，并被配置为处理所述指令的第二指令。第二条指令具有较高的优先级，或要求比第一条指令更快地访问资源。所述装置还包括被配置为对所述第一指令和所述第二指令进行解码并且向所述第一XU发出所述第一指令的反馈引擎，以及被配置为向所述第二XU发送所述第二指令的调度器。

6. 发明申请

WO2015035336A1 METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR PIPELINE AND BYPASS PASSING 审中-公开
标题翻译：用于异步加工管道和旁通管道的方法和装置
公开(公告)号：WO2015035336A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054616
申请日：2014-09-08
申请人： FUTUREWEI TECHNOLOGIES, INC. , HUAWEI TECHNOLOGIES CO., LTD.
发明人： HUANG, Tao , ZHANG, Qifan , SHI, Wuxian , GE, Yiqun , TONG, Wen
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processor comprising a plurality of parallel asynchronous processing logic circuits, each processing logic circuit configured to generate an instruction execution result. The processor comprises an asynchronous instruction dispatch unit coupled to each processing logic circuit, the instruction dispatch unit configured to receive multiple instructions from memory and dispatch individual instructions to each of the processing logic circuits. The processor comprises a crossbar coupled to an output of each processing logic circuit and to the dispatch unit, the crossbar configured to store the instruction execution results.
摘要翻译：一种包括多个并行异步处理逻辑电路的无时钟异步处理器，每个处理逻辑电路经配置以产生指令执行结果。处理器包括耦合到每个处理逻辑电路的异步指令调度单元，所述指令调度单元被配置为从存储器接收多个指令，并向每个处理逻辑电路发送单独的指令。处理器包括耦合到每个处理逻辑电路的输出的交叉开关和分配单元，该交叉开关被配置为存储指令执行结果。

7. 发明申请

WO2015032355A1 SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH MULTIPLE THREADING 审中-公开
标题翻译：具有多路线程的异步处理器的系统和方法
公开(公告)号：WO2015032355A1
公开(公告)日：2015-03-12
申请号：PCT/CN2014/086095
申请日：2014-09-09
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： GE, Yiqun , SHI, Wuxian , ZHANG, Qifan , HUANG, Tao , TONG, Wen
IPC分类号： G06F9/38
CPC分类号： G06F9/3838 , G06F9/3004 , G06F9/30127 , G06F9/3016 , G06F9/3806 , G06F9/3824 , G06F9/3836 , G06F9/3851 , G06F9/3871 , G06F12/0875 , G06F2212/452
摘要： Embodiments are provided for an asynchronous processor with multiple threading. The asynchronous processor includes a program counter (PC) logic and instruction cache unit comprising a plurality of PC logics configured to perform branch prediction and loop predication for a plurality of threads of instructions, and determine target PC addresses for caching the plurality of threads. The processor further comprises an instruction memory configured to cache the plurality of threads in accordance with the target PC addresses from the PC logic and instruction cache unit. The processor further includes a multi-threading (MT) scheduling unit configured to schedule and merge instruction flows for the plurality of threads from the instruction memory into a single combined thread of instructions. Additionally, a MT register window register is included to map operands in the plurality of threads to a plurality of corresponding register windows in a register file.
摘要翻译：为具有多个线程的异步处理器提供实施例。异步处理器包括程序计数器（PC）逻辑和指令高速缓存单元，其包括被配置为对多个指令线程执行分支预测和循环预测的多个PC逻辑，并且确定用于高速缓存多个线程的目标PC地址。处理器还包括指令存储器，其被配置为根据来自PC逻辑和指令高速缓存单元的目标PC地址缓存多个线程。所述处理器还包括多线程（MT）调度单元，其被配置为将所述多个线程的指令流从指令存储器调度并合并成单个组合指令线程。另外，MT寄存器窗口寄存器被包括以将多个线程中的操作数映射到寄存器文件中的多个对应的寄存器窗口。

8. 发明申请

WO2015035333A1 METHOD AND APPARATUS FOR ASYNCHRONOUS PROCESSOR BASED ON CLOCK DELAY ADJUSTMENT 审中-公开
标题翻译：基于时钟延迟调整的异步处理器的方法和装置
公开(公告)号：WO2015035333A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054613
申请日：2014-09-08
申请人： FUTUREWEI TECHNOLOGIES, INC. , HUAWEI TECHNOLOGIES CO., LTD.
发明人： TONG, Wen , GE, Yiqun , ZHANG, Qifan , SHI, Wuxian , HUANG, Tao
IPC分类号： H03K19/096
CPC分类号： G06F9/30145 , G06F1/08 , G06F1/10 , G06F9/30036 , G06F9/30189 , G06F9/3826 , G06F9/3828 , G06F9/3836 , G06F9/3851 , G06F9/3853 , G06F9/3871 , G06F9/3877 , G06F9/3885 , G06F9/3889 , G06F9/3891 , G06F9/5011 , G06F15/8007 , G06F15/8053 , G06F15/8092 , G06F2009/3883
摘要： A clock-less asynchronous processing circuit or system utilizes a self-clocked generator to adjust the processing delay (latency) needed/allowed to the processing cycle in the circuit/system. The timing of the self-clocked generator is dynamically adjustable depending on various parameters. These parameters may include processing instruction, opcode information, type of processing to be performed by the circuit/system, or overall desired processing performance. The latency may also be adjusted to change processing performance, including power consumption, speed etc.
摘要翻译：无时钟异步处理电路或系统利用自定时发生器来调整电路/系统中处理周期所需/允许的处理延迟（等待时间）。自定时发生器的定时可根据各种参数动态调整。这些参数可以包括处理指令，操作码信息，由电路/系统执行的处理类型或整体期望的处理性能。还可以调整延迟以改变处理性能，包括功耗，速度等。

9. 发明申请

WO2015035320A1 SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH A HIERARCHICAL TOKEN SYSTEM 审中-公开
标题翻译：具有分层系统的异步处理器的系统和方法
公开(公告)号：WO2015035320A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054590
申请日：2014-09-08
申请人： HUAWEI TECHNOLOGIES CO., LTD. , FUTUREWEI TECHNOLOGIES, INC.
发明人： GE, Yiqun , SHI, Wuxian , ZHANG, Qifan , HUANG, Tao , TONG, Wen
IPC分类号： H03M7/42
CPC分类号： G06F13/385
摘要： Embodiments are provided for an asynchronous processor with a Hierarchical Token System. The asynchronous processor includes a set of primary processing units configured to gate and pass a set of tokens in a predefined order of a primary token system. The asynchronous processor further includes a set of secondary units configured to gate and pass a second set of tokens in a second predefined order of a secondary token system. The set of tokens of the primary token system includes a token consumed in the set of primary processing units and designated for triggering the secondary token system in the set of secondary units.
摘要翻译：为具有分层令牌系统的异步处理器提供实施例。异步处理器包括一组主处理单元，其被配置为按照主要令牌系统的预定义顺序来选择和传递一组令牌。异步处理器还包括一组辅助单元，其被配置为以辅助令牌系统的第二预定义顺序选通和传递第二组令牌。主令牌系统的令牌集合包括在主处理单元组中消耗的令牌，并被指定用于触发该次要单元组中的辅助令牌系统。

10. 发明申请

WO2015035306A1 SYSTEM AND METHOD FOR AN ASYNCHRONOUS PROCESSOR WITH TOKEN-BASED VERY LONG INSTRUCTION WORD ARCHITECTURE 审中-公开
标题翻译：具有基于非常长的指令字结构的异步处理器的系统和方法
公开(公告)号：WO2015035306A1
公开(公告)日：2015-03-12
申请号：PCT/US2014/054566
申请日：2014-09-08
申请人： HUAWEI TECHNOLOGIES CO., LTD. , FUTUREWEI TECHNOLOGIES, INC.
发明人： GE, Yiqun , SHI, Wuxian , ZHANG, Qifan , HUANG, Tao , TONG, Wen
IPC分类号： G06F15/80
CPC分类号： G06F9/3871 , G06F9/3836 , G06F9/3885 , G06F13/4204 , G06F13/4282
摘要： Embodiments are provided for an asynchronous processor with an asynchronous instruction fetch, decode, and issue unit. The asynchronous processor comprises a memory configured to cache a plurality of instructions, a feedback engine configured to receive the instructions in bundles of instructions at a time and to decode the instructions, and a crossbar bus configured to transfer calculation information and results of the asynchronous processor. The apparatus further comprises a plurality of sets of execution units (XUs) between the feedback engine and the crossbar bus. Each set of the sets of XUs comprises a plurality of XUs arranged in series and configured to process a bundle of instructions received at the each set from the feedback engine.
摘要翻译：为具有异步指令提取，解码和发布单元的异步处理器提供实施例。异步处理器包括被配置为缓存多个指令的存储器，被配置为一次接收指令的指令并且解码指令的反馈引擎以及被配置为传送异步处理器的计算信息和结果的交叉总线。该装置还包括在反馈引擎和交叉开关总线之间的多组执行单元（XU）。每组XU包括串联布置的多个XU并且被配置为处理从反馈引擎在每个集合处接收到的一组指令。

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