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1. 发明专利

JPH0562826B2 失效
公开(公告)号：JPH0562826B2
公开(公告)日：1993-09-09
申请号：JP5462885
申请日：1985-03-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , KONDO SHIZUO , KITAMURA YUKINORI , WATABE TOMOYUKI
IPC分类号： H01L27/082 , H01L21/8226 , H01L27/02

2. 发明专利

JPS62188358A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS62188358A
公开(公告)日：1987-08-17
申请号：JP2882686
申请日：1986-02-14
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAMURA YUKINORI , MAYUZUMI SHIRO , OGURA SADAO , KAMEGAKI KAZUYUKI , MIYAZAKI HIDEO , YAMAZAKI KOICHI
IPC分类号： H01L21/8226 , H01L27/02 , H01L27/082
摘要： PURPOSE:To improve the transmission characteristics of signals by a method wherein, when a vacant space above color regions laid between IIL rows is used as an interconnection region by laying non-diffused regions between color regions below an interconnection region, the parasitic distribution capacity of interconnection connected to the interconnection region is substantially diminished. CONSTITUTION:Multiple rows of IIL arrayed with the gates of multiple IIL are formed; color regions 3 comprising diffused layers are laid between respective IIL rows; a vacant space on a surface insulating film 6 covering the color regions 4 is used as an interconnection region 3. The color regions 4 below the interconnection regions 3 in such a semiconductor integrated circuit device are interrupted by non-diffused regions 41. For example, the non-diffused regions 41 are formed by interrupting the color regions 4 below the interconnection region 3. Said non-diffused regions 41 are not removed of oxide films to form the diffused layers so that the thickness d2 of surface insulating film 6 in that parts may be made larger than the thickness d1 in the color regions 4. Resultantly, overall distribution capacity parasitic on an interconnection 7 alternately passing through both regions 4 and 41 is leveled off in the diminishing direction.

3. 发明专利

JPS6267852A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6267852A
公开(公告)日：1987-03-27
申请号：JP20649185
申请日：1985-09-20
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , KAMEGAKI KAZUYUKI , YAMAZAKI KOICHI , MIYAZAKI HIDEO , KITAMURA YUKINORI , MAYUZUMI SHIRO
IPC分类号： H01L27/082 , H01L21/3205 , H01L21/8226 , H01L23/52 , H01L27/02 , H01L29/41
摘要： PURPOSE:To automatize the design of wiring pattern and to optimize it so as to make the best use of the advantages of I L's, by connecting the I L's with wires arranged at the same pitch as electrodes of the I L. CONSTITUTION:A semiconductor integrated circuit device provided with I L's has first-layer wires Ly juxtaposed in the direction Y, second-layer wires Lx juxtaposed in the direction X orthogonally to the first-layer wires Ly, and through holes TH for connecting the wires Ly in the first layer to the wires Lx in the second layer. Said first-layer wires Ly are located in the first layer in multiple wiring layers and the second-layer wires Lx are located in the second layer therein. By appropriately connecting the first-layer wires Ly and the second-layer wires Lx through the through holes TH, the I L's can be connected with each other by wires arrange regularly.

4. 发明专利

JPH01109761A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH01109761A
公开(公告)日：1989-04-26
申请号：JP26643787
申请日：1987-10-23
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO
IPC分类号： H01L27/04 , H01L21/316 , H01L21/318 , H01L21/822 , H01L21/8222 , H01L27/06
摘要： PURPOSE:To obtain high reliability and high density capacity, by using silicon nitride films having high moisture resistance and high relative permittivity as a protecting film for an active element and a dielectric film for a capacitor element at the same time. CONSTITUTION:A silicon oxide based first insulating film 7 is formed on the main surface of a semiconductor substrate 1. A silicon oxide based second insulating film 9 including phosphorous is formed on the first insulating film 7. The upper part of the second insulating film 9 in an active element region (a) and the first and second insulating films 7 and 9 in a capacitor element region (b) are selectively etched and a hole part 10A is formed. A silicon nitride based third insulating film 13, which has higher moisture resistance, higher heat resistance and relative permittivity higher than those of an SiO2 film, is formed on the hole part 10A. Thus, a protecting film for the active element region and an insulating film (dielectric film) for a capacitor in the capacitor element region are formed at the same time. Thus, high capacity is implemented and moisture resistance is improved. High reliability can be obtained for an IC, which is sealed with plastics.

5. 发明专利

JPS63293969A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS63293969A
公开(公告)日：1988-11-30
申请号：JP12832987
申请日：1987-05-27
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , YAMAGUCHI TAKASHI , YAMAZAKI KOICHI , FUKUDA AKIROU , NAGUMO HIDEKARA , MORI SHUNJI , KAMEGAKI KAZUYUKI
IPC分类号： H01L27/04 , H01L21/822
摘要： PURPOSE:To improve the performance of an IC, and to enhance yield by forming all diffused resistors in the same block in a semiconductor device, in which a plurality of functional blocks are formed on a substrate and circuits including a plurality of the diffused resistors are formed into each block, along one direction on the main surface of the substrate. CONSTITUTION:Various functional blocks 2, 3... are disposed onto one main surface of one semiconductor chip 1, and these functional blocks represent a hand path-amplifier circuit 2, an APC (an auto-phase-control) circuit) 3, a power bias circuit 4, a cross processing circuit 5, etc. in an IC for a television, and circuits having correlation on characteristics such as an AMP 1, an AMP 2, an AMP 3, etc., are includ-. ed in one functional block 2. Accordingly, all resistors determining the characteristics of these circuits are arranged in the same direction in one functional block made up of the circuits having correlation on characteristics, thus acquiring correlation having high accuracy.

6. 发明专利

JPS61218157A RESISTOR 失效
公开(公告)号：JPS61218157A
公开(公告)日：1986-09-27
申请号：JP5841585
申请日：1985-03-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： TAKIGAWA AKIRA , KONDO SHIZUO , KASAHARA MASUMI , HIRASHIMA TOSHINORI , HAIJIMA MIKIO , OGURA SADAO
IPC分类号： H01C7/00 , H01L21/822 , H01L27/04 , H03M1/12
摘要： PURPOSE:To improve the ratio accuracy when a ladder type is particularly formed by forming the corners of a thin film resistor of bent flat pattern at an obtuse angle. CONSTITUTION:A thin film resistor R1 is formed by photoetching a metal resistor 1 made of aluminum or the like in a semiconductor integrated circuit device, and to increase the resistance value, the flat pattern shape is bent in a zigzag shape. The corners 1A, 1B of the pattern are formed at obtuse angle (approx. 135 deg.). Thus, a deformation due to etching is hardly laterally presented, to improve the product accuracy.

7. 发明专利

JPH03126253A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH03126253A
公开(公告)日：1991-05-29
申请号：JP26441489
申请日：1989-10-11
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： NISHIMURA KENJI , AKAMATSU YOSHINORI , OGURA SADAO
IPC分类号： H01L21/8249 , H01L27/06
摘要： PURPOSE:To suppress the operation of a parasitic N-P-N transistor by setting the concentration of the drain of an NMOS at a value higher than the concentration of the source. CONSTITUTION:A P well 13 is formed on a P-type semiconductor substrate 10 at a part where a high breakdown-strength NMOS is formed. Meanwhile, an N type embedded layer 12 and an N-type epitaxial layer 11 which is grown on the N embedded layer 12 are formed on the surface of the P-type semiconductor substrate 1 other than the P well 13. High-concentration N-type drain and source diffused layers 14 and 15 constituting an NMOS are formed on the P well 13 in the aligned pattern. A high-concentration N-type diffused layer 24 is overlapped and formed on the N-type drain diffused layer 14 among the drain and source layers. NMOS gates 16 comprising, e.g. polysilicon are arranged on a gate insulating film 19 between the drain and source diffused layers 14 and 15. All the NMOS gates 16 are formed in a linear state.

8. 发明专利

JPS63107162A VERTICAL TYPE PNP TRANSISTOR 失效
公开(公告)号：JPS63107162A
公开(公告)日：1988-05-12
申请号：JP25170686
申请日：1986-10-24
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： OGURA SADAO , YAMAZAKI KOICHI , TAKAHASHI KENJI , KITAMURA YUKINORI , MORI SHUNJI
IPC分类号： H01L29/73 , H01L21/331 , H01L27/08 , H01L29/72
摘要： PURPOSE:To obtain a transistor characterized by a small occupying area and an excellent current characteristic without a base-current compensating circuit, by forming a p type diffused layer, which is to become a collector, and a p layer, which is to become an emitter in alignment with said p type diffused layer, on the surface of an n-type semiconductor layer, and making a current to flow to the surface side from the inside of a substrate. CONSTITUTION:A p type Si substrate 11, an n embedded layer 12, a p embedded layer 13, a p embedded layer 14 and the like are provided. They are diffused at the same time as the n embedded layer 12 by ion implantation into the surface of the substrate 11. An n-type Si layer 15 is formed thereon by epitaxial growing. A p layer 16, which is to become an emitter lead-out part, and p isolation layers 17 are deeply diffused by simultaneous, selective ion implantation in the surface of the n-type epitaxial layer 15 and connected to the p embedded layers 13 and 14. A plurality of p layers 18, which are to become collectors, are formed over the p embedded layers as shallow diffused layers. A shallow n layer 19, which is to become a base lead-out part, is diffused. Thus multiple collectors are obtained in a small area, and a compact current mirror circuit device is implemented.

9. 发明专利

JPS6318659A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS6318659A
公开(公告)日：1988-01-26
申请号：JP16189986
申请日：1986-07-11
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： KITAMURA YUKINORI , MORI SHUNJI , OGURA SADAO , YAMAZAKI KOICHI , INABA TORU
IPC分类号： H01L27/04 , H01L21/331 , H01L21/337 , H01L21/822 , H01L29/73 , H01L29/732 , H01L29/808 , H01L29/8605
摘要： PURPOSE:To make the resistance value easy to set and variable, by providing electrodes in a first layer of second-conductivity type and a second layer of second-conductivity type, and providing other two electrodes, which hold the second layer of second- conductivity type in the first-conductivity type substrate surrounded by the first layer of second-conductivity type and an embedded layer. CONSTITUTION:On an p type Si semiconductor substrate 1, an n type Si layer 2 is formed by epitaxial growing. An n embedded layer 3 is buried between the substrate 1 and the layer 2. P embedded layers 4 and 5 are formed by implanting p type impurity ions in the surface of the substrate 1 and diffusing the ions in the n-layer after the formation of the epitaxial n layer. A p diffused layer 6 is formed by partially implanting and diffusing ions from the surface of the epitaxial (n) layer. The layer is connected to the embedded layers 4 and 5, and element isolating layers 6 and 5 are formed. A (p) diffused layer 7 is formed on the surface of an (n) layer 2 ', which is to become a resistor region. n diffused layers 8 and 8 are made to be electrode lead-out parts. Thus, the resistor, in which the resistance value can be readily set, and which can be used as a variable resistor by the application of a voltage to the diffused layer 7, can be provided.

10. 发明专利

JPS6252955A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPS6252955A
公开(公告)日：1987-03-07
申请号：JP19194385
申请日：1985-09-02
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： MAYUZUMI SHIRO , KITAMURA YUKINORI , OGURA SADAO , MIYAZAKI HIDEO , KAMEGAKI KAZUYUKI , YAMAZAKI KOICHI
IPC分类号： H01L21/822 , H01L21/8226 , H01L27/04 , H01L27/06 , H01L27/08 , H01L27/082
摘要： PURPOSE:To improve regularity of source-related wirings and facilitate high integrity, high reliability, low cost and so forth by a method wherein analog parts are arranged around a digital part and source trunk lines are provided between those parts. CONSTITUTION:A digital circuit part 3 is provided at the center part of a semiconductor substrate 1 and analog circuit parts 4 are arranged around the digital circuit part 3 and a plurality of source trunk lines L1, L2 and L3 are arranged along the circular part between the digital circuit part 3 and the analog circuit part 4 concentrically and annularly. A main source Vcc, an auxiliary source Vcc/2 and a reference bias source VB are connected to the source trunk lines L1, L2 and L3. The source trunk line L1, through which the largest current flows and which is required to have the lowest impedance, is provided on the innermost side and further, the larger the current flowing through the line, the inner the line is arranged. With this method and annular arrangement, the lower the required impedance, the shorter the wiring distance and the smaller the parasitic impedance. Moreover, the foundation part of the annular region can be utilized as a buffer zone to avoid operational interference between the digital part 3 and the analog parts 4.

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