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1. 发明专利

JPH10215171A PLL CIRCUIT AND RADIO COMMUNICATION TERMINAL EQUIPMENT USING THE CIRCUIT 失效
公开(公告)号：JPH10215171A
公开(公告)日：1998-08-11
申请号：JP1721797
申请日：1997-01-30
申请人： HITACHI LTD , THE TECHNOLOGY PARTNERSHIP PLC
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit for shortening settling time without widening a PLL band and being suitable for being made into an IC. SOLUTION: The phase comparator 1 of this PLL circuit is turned to a current output type and a constant current source 2 is connected to the output terminal of the current output type phase comparator 1 so as to shorten the settling time. Also, the switch 3 for reset of a PLL is connected to the output terminal of the current output type phase comparator 1. Thus, the need of widening the PLL band for shortening the settling time is eliminated and noise is reduced. Also, the switch for the reset and the constant current source for shortening the settling time are made into the IC.

2. 发明专利

SG73493A1 Phase-locked loop circuit and radio communication apparatus using the same 未知
公开(公告)号：SG73493A1
公开(公告)日：2000-06-20
申请号：SG1998000195
申请日：1998-01-26
申请人： HITACHI LTD , THE TECHNOLOGY PARTNERSHIP PLC
发明人： YAMAWAKI TAIZO , KOKOBO MASARU , FURUYA TOMIO , WATANBE KAZUO
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40 , H03C3/09 , H04L7/04 , H04B1/54
摘要： A phase-locked loop circuit includes a current output type phase comparator (1) for converting a phase difference of a first signal (fIN) and a second signal (fREF) into a current signal to be produced, a low pass filter (4) for filtering the current signal of the current output type phase comparator (1) to produce an output signal, a voltage controlled oscillator (5) for producing a signal having a frequency (fRF) corresponding to the output signal of the low pass filter (4) and a frequency converter (7) for frequency-converting the output signal of the voltage controlled oscillator (5) to produce a second signal. A current source (2) is provided for supplying a current which is added to the current signal produced by the phase comparator (1), and the resulting sum current is supplied to an input of the low-pass filter (4). Furthermore a reset switch (3) applies a reset voltage to the voltage controlled oscillator (5) for cancelling a phase-locked state of the phase-lock loop circuit. The phase-locked loop may be used in a transmittor section of a radio communication apparatus, such as a portable terminal of a mobile communication system, to provide for a short frequency settling time and low output noise without broadening of the band of the PLL.

3. 发明专利

NO980399D0 未知
公开(公告)号：NO980399D0
公开(公告)日：1998-01-29
申请号：NO980399
申请日：1998-01-29
申请人： HITACHI LTD , THE TECHNOLOGY PARTNERSHIP PLC
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40 , H03L
摘要： A phase-locked loop circuit includes a current output type phase comparator (1) for converting a phase difference of a first signal (fIN) and a second signal (fREF) into a current signal to be produced, a low pass filter (4) for filtering the current signal of the current output type phase comparator (1) to produce an output signal, a voltage controlled oscillator (5) for producing a signal having a frequency (fRF) corresponding to the output signal of the low pass filter (4) and a frequency converter (7) for frequency-converting the output signal of the voltage controlled oscillator (5) to produce a second signal. A current source (2) is provided for supplying a current which is added to the current signal produced by the phase comparator (1), and the resulting sum current is supplied to an input of the low-pass filter (4). Furthermore a reset switch (3) applies a reset voltage to the voltage controlled oscillator (5) for cancelling a phase-locked state of the phase-lock loop circuit. The phase-locked loop may be used in a transmittor section of a radio communication apparatus, such as a portable terminal of a mobile communication system, to provide for a short frequency settling time and low output noise without broadening of the band of the PLL.

4. 发明专利

NO980399L 未知
公开(公告)号：NO980399L
公开(公告)日：1998-07-31
申请号：NO980399
申请日：1998-01-29
申请人： HITACHI LTD , THE TECHNOLOGY PARTNERSHIP PLC
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40
摘要： A phase-locked loop circuit includes a current output type phase comparator (1) for converting a phase difference of a first signal (fIN) and a second signal (fREF) into a current signal to be produced, a low pass filter (4) for filtering the current signal of the current output type phase comparator (1) to produce an output signal, a voltage controlled oscillator (5) for producing a signal having a frequency (fRF) corresponding to the output signal of the low pass filter (4) and a frequency converter (7) for frequency-converting the output signal of the voltage controlled oscillator (5) to produce a second signal. A current source (2) is provided for supplying a current which is added to the current signal produced by the phase comparator (1), and the resulting sum current is supplied to an input of the low-pass filter (4). Furthermore a reset switch (3) applies a reset voltage to the voltage controlled oscillator (5) for cancelling a phase-locked state of the phase-lock loop circuit. The phase-locked loop may be used in a transmittor section of a radio communication apparatus, such as a portable terminal of a mobile communication system, to provide for a short frequency settling time and low output noise without broadening of the band of the PLL.

5. 发明专利

NO980399A 未知
公开(公告)号：NO980399A
公开(公告)日：1998-07-31
申请号：NO980399
申请日：1998-01-29
申请人： HITACHI LTD , THE TECHNOLOGY PARTNERSHIP PLC
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40
CPC分类号： H03L7/085 , H03L7/10 , H03L7/183 , H03L2207/12 , H04B1/403 , H04B1/408

6. 发明专利

NO318601B1 未知
公开(公告)号：NO318601B1
公开(公告)日：2005-04-18
申请号：NO980399
申请日：1998-01-29
申请人： HITACHI LTD , TTP COMMUNICATIONS LTD
发明人： YAMAWAKI TAIZO , KOKUBO MASARU , FURUYA TOMIO , WATANABE KAZUO , HILDERSLEY JULIAN
IPC分类号： H03L7/085 , H03L7/093 , H03L7/10 , H03L7/183 , H03L7/185 , H04B1/3822 , H04B1/40
摘要： A phase-locked loop circuit includes a current output type phase comparator (1) for converting a phase difference of a first signal (fIN) and a second signal (fREF) into a current signal to be produced, a low pass filter (4) for filtering the current signal of the current output type phase comparator (1) to produce an output signal, a voltage controlled oscillator (5) for producing a signal having a frequency (fRF) corresponding to the output signal of the low pass filter (4) and a frequency converter (7) for frequency-converting the output signal of the voltage controlled oscillator (5) to produce a second signal. A current source (2) is provided for supplying a current which is added to the current signal produced by the phase comparator (1), and the resulting sum current is supplied to an input of the low-pass filter (4). Furthermore a reset switch (3) applies a reset voltage to the voltage controlled oscillator (5) for cancelling a phase-locked state of the phase-lock loop circuit. The phase-locked loop may be used in a transmittor section of a radio communication apparatus, such as a portable terminal of a mobile communication system, to provide for a short frequency settling time and low output noise without broadening of the band of the PLL.

7. 发明专利

JPS61245627A OSCILLATING CIRCUIT 失效
公开(公告)号：JPS61245627A
公开(公告)日：1986-10-31
申请号：JP8644085
申请日：1985-04-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： FURUYA TOMIO
IPC分类号： H03B5/12 , H03B5/02 , H03L5/00 , H04B1/26
摘要： PURPOSE:To obtain the stable oscillation output over a wide frequency range by converting the oscillation output into a DC signal by a wave detecting circuit, comparing the DC signal with the reference voltage and increasing the gain of an oscillating circuit via a control circuit when the oscillation output is reduced to less than a prescribed level. CONSTITUTION:A frequency signal fL is supplied to a wave detecting circuit 5 and converted into a DC signal VC. Then the signal fL is turned into a high frequency, and the level of the signal VC is reduced in proportion to the reduction of the amplitude level of said high frequency. Then Vref>VC is satisfied and the output voltage VA is changed to a high level. Thus a transistor TR Q3 of an oscillating circuit 4 is turned on and the voltage drop due to a resistance R1 is increased in response to the increase of a current. Thus the amplitude degree is increased. As a result, the amplitude of the signal fL is not reduced even through a high frequency exceeds a prescribed frequency level. Then an approximately fixed amplitude level can be kept between the low and high frequency areas.

8. 发明专利

JPS59182612A Am receiver 失效
标题翻译：接收器
公开(公告)号：JPS59182612A
公开(公告)日：1984-10-17
申请号：JP5514483
申请日：1983-04-01
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： FURUYA TOMIO
IPC分类号： H04N5/52 , H03G3/20 , H04B1/16
CPC分类号： H03G3/3052
摘要： PURPOSE:To quicken a response speed and also to obtain an output signal with low distortion factor by controlling automatically the gain of an AM amplifier circuit with priority over others when a level change of an AM input signal reaches a prescribed level or over. CONSTITUTION:Even if the level of an input signal fs is increased rapidly, since the output impedance of an emitter follower transistor (TR) Q103 charging a capacitor of large capacitance is small, an RFAGC responds to a rapid and excessive level fluctuation of the signal fs. Further, a circuit block 19 eliminates pop noises at the application of power supply, acts like an initializing circuit, and the AGC appears at a line l1 at the application of power supply, thereby performing temporary AGC operation. Moreover, the voltage at a terminal 14 rises according to the time constant comprising a resistor R54 and a capacitor C23 after application of power supply, interrupting an AGC signal on the line l1 and eliminating the RFAGC. Since the RFAGC is applied temporarily, generation of pop noises is prevented.
摘要翻译：目的：当AM输入信号的电平变化达到规定水平或以上时，通过自动控制AM放大器电路的增益优先于其他方式，以加快响应速度，并获得具有低失真因数的输出信号。构成：即使输入信号fs的电平快速增加，由于对大容量的电容器充电的射极跟随晶体管（TR）Q103的输出阻抗小，因此RFAGC对信号的快速和过大的电平波动进行响应 FS。此外，电路块19消除了在施加电源时的弹性噪声，起到初始化电路的作用，并且AGC在施加电源时出现在线路l1处，从而执行临时AGC操作。此外，在施加电源之后，端子14处的电压根据包括电阻器R54和电容器C23的时间常数上升，中断线路11上的AGC信号并消除RFAGC。由于暂时应用RFAGC，因此防止弹奏噪声的产生。

9. 发明专利

JPH053443A FM RADIO RECEIVER 失效
公开(公告)号：JPH053443A
公开(公告)日：1993-01-08
申请号：JP18024691
申请日：1991-06-25
申请人： VICTOR COMPANY OF JAPAN , HITACHI LTD , HITACHI MICOM SYST KK
发明人： MAEDA NOBUO , IENAKA MASANORI , FURUYA TOMIO
IPC分类号： H04B1/10
摘要： PURPOSE:To realize the FM radio receiver in which reproduction with high fidelity is implemented in an excellent reception state when no adjacent disturbance is received in the FM radio receiver of the double superheterodyne system provided with a 1st intermediate frequency amplifier stage and a 2nd intermediate frequency amplifier stage having a narrower frequency band than that of the 1st intermediate frequency amplifier stage. CONSTITUTION:The radio receiver is provided with a 1st intermediate frequency signal demodulation section 11 and a 2nd intermediate frequency signal demodulation section 35 demodulating respectively output signals 7a, 35a of 1st and 2nd intermediate frequency amplifier stages. A demodulation signal selection control circuit 13 controls a demodulation signal selection circuit 13 to select a demodulation output 11a of the 1st intermediate frequency signal demodulation section 11 when reception state is excellent based on outputs of signal level detection circuits 30, 32 of a reception station and an adjacent station.

10. 发明专利

JPS60177734A RECEIVER 失效
公开(公告)号：JPS60177734A
公开(公告)日：1985-09-11
申请号：JP3243984
申请日：1984-02-24
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： FURUYA TOMIO , OOKUBO YUUICHI
IPC分类号： H04B1/16
摘要： PURPOSE:To make it unnecessary to adjust the gain of an intermediate frequency amplifying circuit, and also to decrease external parts of an IC by constituting the itermediate frequency amplifying circuit of an amplifier whose gain is determined without depending on an error of a resistance value formed in the inside of the IC, and a ceramic filter. CONSTITUTION:An output of a mixing circuit 3 is supplied to an intermediate frequency transformer of a wide band consisting of a capacitor C12 and coils L12, L13, and an intermediate frequency signal If is obtained. The signal If is supplied further to an amplifier A through a ceramic filter 5. The frequency characteristic of this filter 5 is a narrow band, and its adjusting work is not required. As for the amplifier A, when a receiving radio wave is a weak electric field, an amplifying circuit with high gain is constituted of transistors Q11, Q13 and Q14, and when the receiving radio wave goes to strong electric field intensity, an amplifying circuit of a low gain is constituted of transistors Q12, Q15 and Q16, and resistances R11, R12, and the second amplifying circuit is constituted of transistors Q17-Q20. The total gain of the amplifier A is determined by scarcely depending on the error of resistance value of the inside of an IC, a load is only a resistance R1, and no amplification degree is varied.

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