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1. 发明专利

JPS6449326A OFF-SET COMPENSATING CIRCUIT 失效
公开(公告)号：JPS6449326A
公开(公告)日：1989-02-23
申请号：JP20503487
申请日：1987-08-20
申请人： PIONEER ELECTRONIC CORP , HITACHI LTD
发明人： TSUCHIDA MASAMI , ISO YOSHIMI
IPC分类号： H03M1/10
摘要： PURPOSE:To execute exact off-set compensation in the same way at the time of no-signal input even at the time of an input signal impressing by storing the value of a proper off-set correcting voltage at the time of the no-signal input to a memory means and compensating an off-set based on the off-set correcting voltage stored at the time of the input signal impressing of a music signal, etc. CONSTITUTION:At the time of the no-signal input, a switch means 6 is in a contact (a) side and the proper off-set correcting voltage obtained from an integrator 3 is fed-back through a filter 4. Then, the off-set compensation is executed. Simultaneously, the off-set correcting voltage from the integrator 3 at the time of the no-signal input is supplied to a memory means 5 and stored here. At the time of the input signal impressing, the switch means 6 is changed- over to a contact (b) side and the proper off-set correcting voltage at the time of the no-signal input stored to the memory means 5 is returned through the filter 4. Then, the off-set compensation of a circuit system is executed. Thus, the malfunction of an off-set compensating circuit, which is occurred since a type of instruments is not generated at a positive and negative equal probability, is prevented.

2. 发明专利

JPS6449322A A/D AND D/A CONVERTING CIRCUIT 失效
公开(公告)号：JPS6449322A
公开(公告)日：1989-02-23
申请号：JP20504387
申请日：1987-08-20
申请人： PIONEER ELECTRONIC CORP , HITACHI LTD
发明人： WAKUMURA SHINICHI , TSUCHIDA MASAMI , OKAMOTO HIROO , ISO YOSHIMI
IPC分类号： H03M1/02
摘要： PURPOSE:To widely reduce a circuit scale and to reduce power consumption by providing a shift register and a counter which can be shared respectively with an A/D convertor and a D/A convertor. CONSTITUTION:A current voltage converting circuit 104 is grounded by a non- inverted input and composed of an operational amplifier 104a in which a feedback resistance 105 is connected between an inverted input and an output. An input switch S11 is controlled by a mode signal inputted to a control input terminal 106, turned on with an A/D converting mode and turned off with a D/A converting mode. An aperture switch S16 is controlled by the mode signal inputted to a control input terminal 118, turned off with the A/D converting mode and turned on for a prescribed time so as to sample only a proper D/A converting value out of an integration output voltage with the D/A converting mode. The output of a mirror integration amplifier 110 is also supplied to a level comparator 119 with the A/D converting mode and compared with prescribed levels V1-V3 here. Thus, the circuit scale can be reduced and the power consumption can be decreased.

3. 发明专利

JPS6444123A PLL CIRCUIT 失效
公开(公告)号：JPS6444123A
公开(公告)日：1989-02-16
申请号：JP19987587
申请日：1987-08-12
申请人： HITACHI LTD , PIONEER ELECTRONIC CORP
发明人： TAKADA HIDEAKI , ISO YOSHIMI , INOHANA HARUYUKI , TSUCHIDA MASAMI
IPC分类号： H03L7/10
摘要： PURPOSE:To obtain a clock signal synchronously with an input signal stably by providing a reset circuit to a voltage controlled oscillator, and resetting the oscillator when the input signal and the output clock signal of the oscillator are not synchronized. CONSTITUTION:An input signal supplied to an input terminal 1 and an output clock signal of a voltage controlled oscillator VCO 4 are fed to a phase comparator 2, and the output signal of the phase comparator 2 is fed to the VCO 4 via a low pass filter 3 to apply PLL operation. A reset circuit is provided to the VCO 4 and when the input signal and the clock signal are not synchronized, the VCO 4 is reset by a reset pulse generated from a reset pulse generating circuit 5. Thus, even when the repetitive period of the output waveform of the comparator 2 is smaller than the time constant of the filter 3, the PLL does not reach a pseudo stable state and the clock signal synchronously with the input signal is obtained stably.

4. 发明专利

JPS6449327A INTEGRATION TYPE A/D CONVERTOR 失效
公开(公告)号：JPS6449327A
公开(公告)日：1989-02-23
申请号：JP20502487
申请日：1987-08-20
申请人： PIONEER ELECTRONIC CORP , HITACHI LTD
发明人： TSUCHIDA MASAMI , WAKUMURA SHINICHI , ISO YOSHIMI
IPC分类号： H03M1/52
摘要： PURPOSE:To prevent a malfunction due to the noise of a beardshape to be generated to the output of an integrator at the time of the closing and opening of a reference current source by prohibiting the change of a counting operation condition after the closing of the reference current source or only for a prescribed time after the opening so that a counting condition in a counter can not be changed. CONSTITUTION:A prohibiting circuit 22 is provided between the outputs of comparators 11 and 12 and a control circuit 14 and the prohibiting operation of the prohibiting circuit 22 is controlled by the control circuit 14. A comparator prohibiting signal is transmitted from the prohibiting circuit 22 only for a constant time after a switch 7 is closed. Inversely, even when the switch 7 is opened, the comparator prohibiting signal is transmitted from the prohibiting circuit 22 only for the constant time. Thus, even when the noise of the beard-shape is generated to the output of a differential amplifier 4 to constitute the integrator and the output of a differential amplifier 12 to constitute the comparator is inverted, the output from the differential amplifier 12 is prohibited to be supplied to the control circuit 14 by the comparator prohibiting signal generated in the prohibiting circuit 22. At a time point a prohibiting period ends, since the noise of the beard-shape is erased, the proper counting operation is executed in the counter.

5. 发明专利

JPS6449323A OFF-SET COMPENSATING CIRCUIT 失效
公开(公告)号：JPS6449323A
公开(公告)日：1989-02-23
申请号：JP20503187
申请日：1987-08-20
申请人： PIONEER ELECTRONIC CORP , HITACHI LTD
发明人： TSUCHIDA MASAMI , MIYAKE ICHIRO , TAKAHASHI TOKIHIRO , WAKUMURA SHINICHI , ISO YOSHIMI , ARAI TAKAO , OKAMOTO HIROO
IPC分类号： H03M1/10
摘要： PURPOSE:To execute exact oft-set compensation even to an input signal which is not realized in a positive and negative nonsynmmetric waveform or a positive and negative equal probability by adding not only the code bit of digital data but also the amplitude information of an input analog signal as a control signal in an off-set compensating circuit. CONSTITUTION:For an input analog signal IN, only a necessary band component is removed by a filter 4 and supplied to an A/D convertor 1 and outputted as a digital signal output OUT by this A/D convertor 1. A PWM wave is prepared to correspond to the data of high order side (m) of the digital signal output OUT by a pulse width modulating wave generating means 5. This PWM wave is supplied to an integrator 3 and an off-set correcting voltage VCMP is prepared here. Then, this off-set correcting voltage VCMP is fed-back through the filter 4 and the off-set compensation of the above-mentioned circuit system is executed.

6. 发明专利

JPS6449318A ANALOG SWITCH CIRCUIT 失效
公开(公告)号：JPS6449318A
公开(公告)日：1989-02-23
申请号：JP20503087
申请日：1987-08-20
申请人： PIONEER ELECTRONIC CORP , HITACHI LTD
发明人： TSUCHIDA MASAMI , ISO YOSHIMI
IPC分类号： G06F3/05 , G11C27/02 , H03K17/14 , H03K17/60 , H03M1/02
摘要： PURPOSE:To prevent the inversion of a switching sequence of a transistor and to execute an exact switching control by making the timing of cut-off in an npn type transistor and a pnp type transistor for constituting an output circuit different from each other. CONSTITUTION:A timing circuit 5 generates a timing signal for control transistors(TRs) Q3, Q6, TRs Q4, Q5, respectively, by allowing it to have a necessary time difference, at the time of A/D and D/A, based on a sample-hold pulse. The control of ON/OFF of an npn type TR Q1 is executed, based on the control of the TRs Q4, Q5, and the control of ON/OFF of a pnp type TR Q2 is executed by an exclusive cut-off means, respectively, based on the control of the TR Q6. Also, said timing of ON/OFF can be determined in advance by the timing circuit 5. In such a way, from a base voltage of the TRs Q1, Q2 of an output circuit at the time of the sample-hold of A/D and the timing of cut-off, the pnp type TR Q2 is cut off by preceding by about 200ns with respect to the npn type TR Q1.

7. 发明专利

JPS6444131A A/D CONVERTER 失效
公开(公告)号：JPS6444131A
公开(公告)日：1989-02-16
申请号：JP19985787
申请日：1987-08-12
申请人： HITACHI LTD , PIONEER ELECTRONIC CORP
发明人： ISO YOSHIMI , TSUCHIDA MASAMI
IPC分类号： H03M1/52
摘要： PURPOSE:To ensure the linearity of conversion by supplying a power from an analog power supply to the pre-stage of a comparator and supplying power supply from a digital power supply to the post-stage of the comparator so as to separate a comparison voltage from noise of a digital part. CONSTITUTION:When a voltage corresponding to an analog signal given to a terminal 1 is held in a capacitor 6, switches 11, 12 are closed and a constant current is supplied from constant current circuits 13, 14 to the capacitor 6 to start integration. Then the voltage of the capacitor 6 is compared with the comparison level from a comparison level generating circuit 10 by comparators 18, 19 and the period till the output of the comparators 18, 19 is inverted is counted by counters 21, 22 to obtain a digital value. In this case, power is supplied to pre-stages 31, 33 of the comparators 18, 19 from the analog power supply 35 and power is supplied to the post-stages 32, 34 of the comparators 18, 19 from the digital power supply 37, then the said comparison level is separated from the noise of the digital part to ensure the linearity of conversion.

8. 发明专利

JPS6444130A A/D CONVERTER 失效
公开(公告)号：JPS6444130A
公开(公告)日：1989-02-16
申请号：JP19985587
申请日：1987-08-12
申请人： HITACHI LTD , PIONEER ELECTRONIC CORP
发明人： ISO YOSHIMI , TSUCHIDA MASAMI
IPC分类号： H03M1/52
摘要： PURPOSE:To eliminate the deterioration in the conversion linearity against the dispersion in the reference voltage, and temperature/power supply voltage fluctuation by giving a correlation to a midpoint potential of an integration type A/D converter of a single power supply, a comparison level potential and an integration current. CONSTITUTION:When a voltage corresponding to an analog signal inputted to a terminal 1 is held in an integration capacitor 66, switches 11, 12 are closed and a constant current is supplied from a constant current circuit 30 to the capacitor 6 and integration is started. Then the voltage of the capacitor 6 is compared with a comparison level from a comparison level generating circuit 10 by comparators 18, 19 an the period till the output of the comparators 18, 19 is inverted is counted by counters 21, 22 to obtain a digital value. In this case, since constant voltage source circuits 8, 9 decides a voltage to be supplied to the circuit 10, a midpoint potential with reference to the output potential of reference power supplies 28 and a voltage supplied to a voltage-current conversion circuit 29 controlling the reference current of the circuit 30, the correlativity is given to the midpoint potential, the comparison level and the integration current.

9. 发明专利

JPS6444129A A/D CONVERTER 失效
公开(公告)号：JPS6444129A
公开(公告)日：1989-02-16
申请号：JP19985487
申请日：1987-08-12
申请人： HITACHI LTD , PIONEER ELECTRONIC CORP
发明人： ISO YOSHIMI , TSUCHIDA MASAMI
IPC分类号： H03M1/52
摘要： PURPOSE:To ensure sufficient dynamic range even with a low voltage by inputting a signal with respect to a center potential of a reference voltage to an integration device and a circuit of the pre-stage of the integration device and level-shifting an output of the integration device. CONSTITUTION:When a voltage corresponding to an input analog signal is held in an integration capacitor 6 via a buffer amplifier 2, switches 11, 12 are closed and a constant current is fed from constant current circuits 13, 14 to the capacitor 6 to start integration. Then the voltage being the result of level- shift of the voltage of the capacitor 6 by the circuit 26 is compared with a level being the result of level shift of the comparison level from a comparison level generating circuit 10 at the circuits 27, 28 by the same level as that of the circuit 26 by comparators 18, 19 and the period till the output of the comparators 18, 19 is inverted is counted by the counters 21, 22 to obtain a digital value. In this case, since the integration capacitor 6 and the circuit of the pre-stage act on the center value of the power voltage, the dynamic range is used to pass the signal.

10. 发明专利

JPS6444110A AMPLIFIER 失效
公开(公告)号：JPS6444110A
公开(公告)日：1989-02-16
申请号：JP19985187
申请日：1987-08-12
申请人： HITACHI LTD , PIONEER ELECTRONIC CORP
发明人： ISO YOSHIMI , TSUCHIDA MASAMI
IPC分类号： H03G3/10 , H03F3/34 , H03F3/343 , H03F3/45
摘要： PURPOSE:To approach an input bias current zero by providing a gain adjusting circuit or a base current cancel circuit to a current mirror circuit so as to correct the decrease in the cancelling current. CONSTITUTION:A transistor(TR) 45 becomes a pseudo input TR in a base current compensation circuit 25. Then a TR 44 giving an identical current to that of a TR 2 is provided so as to cause an identical current to flow to TRs 31, 45. A means detecting the base current of the TR 45 is a diode 46. Then a diode 61 and a resistor 62 constitute a level shift circuit and the base potential of the TR 45 is decided via the base-emitter voltage of resistors 51, 62 and TRs 48, 52, 61, 46. Moreover, a base drive TR 52 is provided to TRs 48, 49 of the current mirror circuit. Moreover, a TR 63 is provided in series with the TR 52 and the base current is added to the collector of the output TR 49 to make the input bias current zero.

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