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1. 发明专利

JPH1167626A METHOD AND DEVICE FOR REMOVING RESIST 失效
公开(公告)号：JPH1167626A
公开(公告)日：1999-03-09
申请号：JP21735897
申请日：1997-08-12
申请人： HITACHI LTD , NITTO DENKO CORP
发明人： SHIRAI SEIICHIRO , ONOZUKA TOSHIHIKO , NOISSHIKI TAKAYUKI , SAKAI SATORU , SASAJIMA KATSUHIRO , TOYODA HIDESHI , NAMIKAWA AKIRA
IPC分类号： C09J7/00 , C09J5/00 , G03F7/34 , G03F7/42 , H01L21/027 , H01L21/311
摘要： PROBLEM TO BE SOLVED: To readily perform the removal of a resist film, without imparting damages to a gate oxide film. SOLUTION: In a semiconductor water 1 on which many kinds of gate oxide films 2 are formed, a resist film 3 as a mask when the unnecessary part of the gate oxide film 2 is etched is formed on the gate oxide film 2 formed on the semiconductor wafer 1. With the resist film 3 as a mask, the unnecessary part of the gate oxide film 2 is etched. Thereafter, the resist film 3 is removed by an adhesive cape 4. Thus, the first gate oxide film 2 is formed on the semiconductor wafer 1. Thereafter, the second gate oxide film 2 is formed at the upper layer of this first gate oxide film 2.

2. 发明专利

JP2000306896A METHOD AND APPARATUS FOR MANUFACTURING SEMICONDUCTOR DEVICE 失效
公开(公告)号：JP2000306896A
公开(公告)日：2000-11-02
申请号：JP11706899
申请日：1999-04-23
申请人： HITACHI LTD
发明人： SASAJIMA KATSUHIRO , FUNATSU YOSHIAKI
IPC分类号： H01L21/302 , H01L21/027 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To remove a resist film formed on a surface of a metal pattern. SOLUTION: A discharge tube 33, hung from the top in a treatment chamber 31 of an ozone ashing device 30 performing a sub-ashing process, blows out an ashing gas containing ozone (O3) as main component like a shower outward in the diameter direction. A wafer 50 is held on a susceptor 37 provided at the bottom of the treatment chamber 31. A heater 38, provided concentrically outside the susceptor 37, heats only the outer periphery of the wafer 50. The susceptor 37 is rotated by a rotational shaft 39. The treatment chamber 31 is evacuated by an exhaust port 40. Since only the periphery of the wafer is heated, the ashing gas is supplied only to the periphery of the wafer, while oxidation of the surface of Cu wiring in the central portion and residues of the resist film in the periphery can be surely removed by ashing.

3. 发明专利

JPH09213793A SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND MANUFACTURE THEREOF 失效
公开(公告)号：JPH09213793A
公开(公告)日：1997-08-15
申请号：JP1694996
申请日：1996-02-02
申请人： HITACHI LTD
发明人： SASAJIMA KATSUHIRO , TOKUNAGA TAKAFUMI
IPC分类号： H01L21/28 , H01L21/336 , H01L21/768 , H01L29/78
摘要： PROBLEM TO BE SOLVED: To reduce process failure in a multilayer wiring without degrading reliability of a semiconductor device in a semiconductor integrated circuit device having a multilayer wiring. SOLUTION: A stopper silicon nitride film 11 is provided between a first-layer wiring 14 and a BPSG film 10. The silicon nitride film 11 stops etching of an interlayer dielectric film 15 upon formation of a through hole 16, which prevents etching of the BPSG film 10 and a silicon oxide film 9 positioned below the first-layer wiring 14. Further, since the stopper silicon nitride film 11 is provided only in a region where the through hole 16 is formed, hydrogen, which is introduced by hydrogen annealing treatment performed on a semiconductor substrate 1 after formation of a second-layer wiring 17, easily reaches the interface of a gate insulating film 4 and the semiconductor substrate 1. This reduces the interface levels.

4. 发明专利

JPH1130687A DISPLAY DEVICE 失效
公开(公告)号：JPH1130687A
公开(公告)日：1999-02-02
申请号：JP18480097
申请日：1997-07-10
申请人： HITACHI LTD , HITACHI ENG CO LTD
发明人： SAITO HIDENORI , KUBOTA RYUJI , SATO HIROYUKI , KASANO TOSHIO , SASAJIMA KATSUHIRO
IPC分类号： G21C17/00
摘要： PROBLEM TO BE SOLVED: To provide a large display device enabling an operator to grasp a plant operating state in a short time from any position in a central control room of an existing BWR plant. SOLUTION: A large display board with a large mimic fixed display part 6 is additionally provided in dead space confirmable by an operator in a central control room in a plant so that the operator can grasp the operating state of the plant in a short time from any position. Since it is difficult to remodel an existing relay type controller, system constitution is so formed as to supply information to be displayed on the large display board by batch-controlling contents to be displayed in a large display device by one display control device from a process computer system 2 receiving equipment control signals concentrated thereon from relay type controllers 11 of each system and controlling information to be displayed on the image plane of CRTs 9.

5. 发明专利

JPH10270424A METHOD OF FORMING SEMICONDUCTOR ELEMENT PATTERN 失效
公开(公告)号：JPH10270424A
公开(公告)日：1998-10-09
申请号：JP7498597
申请日：1997-03-27
申请人： HITACHI LTD
发明人： KAWASAKI HIROMICHI , TSUNEKAWA SUKEYOSHI , FUNATSU YOSHIAKI , SASAJIMA KATSUHIRO , INADA YOSHIKAZU , KATSUYAMA KIYOMI
IPC分类号： H01L21/302 , H01L21/027 , H01L21/3065
摘要： PROBLEM TO BE SOLVED: To form a clean surface without hydrophobic residues by using an etching gas which will form F-contg. polymers for dry etching a silicon oxide or silicon nitride base layer and removing a resin photo mask having no polymer by the ozone ashing. SOLUTION: To form desired pattern of an Si nitride film on a semiconductor wafer, an org. polymer resist is applied to form a resist layer on desired element pattern by exposure and development. Using the resist as a mask it is dry etched with an etching gas at least contg. CHF3 , though the gas is not limited to CHF3 . The used mask is removed by the ozone ashing, thereby reducing the F content remaining on a base film surface.

6. 发明专利

JPH10223753A MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE AND SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH10223753A
公开(公告)日：1998-08-21
申请号：JP2304197
申请日：1997-02-05
申请人： HITACHI LTD
发明人： SASAJIMA KATSUHIRO
IPC分类号： H01L23/522 , H01L21/768
摘要： PROBLEM TO BE SOLVED: To prevent the generation of the reaction product of an etching gas with Ti by a method wherein, when a connecting hole is bored in an insulating film, a protective conductor layer which prevents a part of a conductor layer containing Ti from being exposed from the connecting hole is formed on the conductor layer which is formed in the upper-layer part of a lower-layer interconnection and which contains Ti. SOLUTION: An insulating film 2 is deposited on a semiconductor substrate 1, conductor layers 3L1a to 3L1c are deposited on the surface of the insulating film 2 by a sputtering method or the like, a conductor layer 3L1d which is composed of Al or an Al alloy is deposited on the conductor layer 3L1c by a sputtering method or the like, and first-layer interconnection 3L1 is formed. In addition, an insulating film 4a is formed so as to cover the first-layer interconnection 3L1 , a connecting hole which exposes a part of the conductor layer 3L1c at the first-layer interconnection 3L1 is bored in the insulating film 4a by an etching treatment using a fluorine-based gas, and the uppermost conductor layer 3L1d protects a part of the conductor layer 3L1c from being exposed.

7. 发明专利

JPH1079480A MANUFACTURING SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE 失效
公开(公告)号：JPH1079480A
公开(公告)日：1998-03-24
申请号：JP23534296
申请日：1996-09-05
申请人： HITACHI LTD
发明人： SASAJIMA KATSUHIRO
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/108
摘要： PROBLEM TO BE SOLVED: To prevent the over-etching of the bottoms of connecting holes each of which has a small aspect ratio for connecting an upper and lower wirings, when these connecting holes and connecting holes for connecting the wirings and semiconductor elements are formed simultaneously. SOLUTION: A DRAM has information-storing capacitive elements C with a silicon oxide film 37 deposited on the tops of these elements. This film 37 is simultaneously etched to form connecting holes 38-42 into the tops of plate electrodes 34 and MISFETs (n- and p-channel MISFET Qns and Qps) of the peripheral circuit. To do this, plugs 29 are previously formed at the bottoms of the connecting holes 39-42 of the peripheral circuit to avoid causing large differences between the aspect ratios of the connecting holes 38 at the tops of the capacitive elements C and those of 39-42 at the tops of the MISFETs of the peripheral circuits.

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