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1. 发明专利

JPS61224523A SIGNAL TRANSMISSION CONFIRMING SYSTEM 失效
公开(公告)号：JPS61224523A
公开(公告)日：1986-10-06
申请号：JP6359185
申请日：1985-03-29
申请人： HITACHI LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD , NEC CORP , FUJITSU LTD
发明人： HASHIMOTO MASASHI , AOKI SEIJI , HOSHI SHINJI , MIURA OSAMU , KODA YOSHIFUMI
IPC分类号： H04B3/46 , H04Q1/20
摘要： PURPOSE:To simplify and economize the device by sending a signal of ground level or its equivalent to a specified lead of a connector from the sending side, using the signal returned at the sending side so as to detect the normality of connection of the connector, thereby confirming the signal transmission and detecting easily the normality of the connection of transmission/reception side connectors. CONSTITUTION:A ground signal of a lead 10, e.g., is sent to a specified lead of a transmission side connector via a driver 1 from the sending side A, the signal is returned to the device A via a receiver 2 of the reception side and the returned signal is inputted to a fault information detection circuit 9 as a signal CN. When the transmission/reception side connectors 5-8 are connected normally and the reception side device B exists, a fault signal AL of the fault information detection circuit 9 using '0' level of the designation signal B of the device B sent from a controller CONTA of the device A via a lead 11 and a connection lead 13 and '0' level of the returned signal CN as two inputs goes to '1', the signal is sent to the controller CONTA via a lead 14 so as to inform that the information transmission/reception is normal to the controller CONTA.

2. 发明专利

JPS62276647A MEMORY PROTECTING SYSTEM 失效
公开(公告)号：JPS62276647A
公开(公告)日：1987-12-01
申请号：JP12073986
申请日：1986-05-26
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE , OKI ELECTRIC IND CO LTD
发明人： KODA YOSHIFUMI , KOMATSUBARA TSUTOMU , FUTAGAWA TAKESHI
IPC分类号： G06F12/14 , G06F21/24
摘要： PURPOSE:To attain various access requests and to protect data in a memory as much as possible by inhibiting access only to an area setting up previously fixed locking information in a memory. CONSTITUTION:An information processing system allows access requests having keys coincident with locking information L1-Ln to access respective areas A1-An. An access inhibiting means 200 inhibits an access request to an area Ai setting up lock information Lm previously fixed in a locking information setting means 100. In addition, the means 200 allows an access request having a previously fixed key kh to access to all the areas A1-An in the memory 4.

3. 发明专利

JPS62273692A MEMORY ACCESS SYSTEM 失效
公开(公告)号：JPS62273692A
公开(公告)日：1987-11-27
申请号：JP11658986
申请日：1986-05-21
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KODA YOSHIFUMI , KOMATSUBARA TSUTOMU
IPC分类号： G11C7/00 , G06F12/02
摘要： PURPOSE:To attain the effective utilization of a memory device by checking the propriety of data consecutive read based on an input address and an address number at a nibble control means and returning the discriminating result to an access side device. CONSTITUTION:A low-order 2-bit of an address (a) inputted from an access device 1 to a nibble memory 2 is inputted to a nibble discrimination circuit 6. The device 1 desiring 2-word consecutive read sends the address (a) to the memory 2 and sends an address number n1 to the discrimination circuit 6 respectively. When the number n1 is 2-word, the discrimination circuit 6 checks whether or not the low-order 2-bit of the address (a) is '11', and in case of not '11', a start signal e1 and an enable word number n2 are sent to a control circuit 3, which generates a timing signal required for the 2-word consecutive read and sent to the memory 2 via a gate 5. As a result, storage data (d) at addresses (a), a+1 are read sequentially from the memory 2 and returned to the device 1.

4. 发明专利

JPH03293837A BUS TRANSFER CONTROL SYSTEM 失效
公开(公告)号：JPH03293837A
公开(公告)日：1991-12-25
申请号：JP9498390
申请日：1990-04-12
申请人： NIPPON TELEGRAPH & TELEPHONE , FUJITSU LTD
发明人： OKAMOTO HISASHI , WAKIMURA YOSHIAKI , OKAZAKI MAKOTO , KODA YOSHIFUMI
IPC分类号： G06F13/362 , H04L12/40
摘要： PURPOSE:To prevent disappearance of write data by exclusively performing the continuous access from another device with respect to a bus of the split transfer system. CONSTITUTION:When detecting command reception of a continuous access request by a bus lock signal 61, a memory device 21 does not acquire the bus access right and sends answer data stored in a transmission buffer 212 till them to a common bus 51. Next, the memory device 21 returns answer data to the read command from a processor 11 to the processor 11. When receiving answer data from the memory device 21, the processor 11 judges the end of discharge processing of a reception buffer 211 and the transmission buffer 212 in the memory device 21 and performs the next continuous access to the memory device 21 thereafter. Thus, disappearance of write data is prevented.

5. 发明专利

JPS61224591A DIGITAL EXCHANGE SYSTEM 失效
公开(公告)号：JPS61224591A
公开(公告)日：1986-10-06
申请号：JP6336285
申请日：1985-03-29
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KODA YOSHIFUMI , OKAMOTO HISASHI
IPC分类号： H04Q3/545 , H04M3/24 , H04Q1/20 , H04Q3/60
摘要： PURPOSE:To obtain the master processor and the standby processor of a processor system in a slave station side with an individually and simple constitution at the slave station side. CONSTITUTION:When a processor system equipment 1 of a master station side is broken down, a master processor 21 continues to operate as usual. When the processor 21 is troubled, a differentiation circuit 203 is detected and a pulse signal is outputted. At a switching processing circuit 205, a switching control signal SWC is impressed at a standby processor 22 responding to the input pulse. Responding to the switching control signal SWC, the standby processor 22 is operated. As the standby processor 22 can identify whether a backup processing is requested upon the switching control signal SWC, or is requested by the command from the processor system device 1 of the master station side, the backup processing corresponding to the difference of the command is executed.

6. 发明专利

JPH08314764A BUS TRACER 失效
公开(公告)号：JPH08314764A
公开(公告)日：1996-11-29
申请号：JP11805695
申请日：1995-05-17
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： ARAI TAKASHI , NAKAMURA MASAKAZU , NAGABORI KAZUO , KODA YOSHIFUMI , MIKI SHUJI
IPC分类号： G06F11/28 , G06F11/34
摘要： PURPOSE: To effectively use memory for trace and to efficiently accumulate trace data with a memory small in capacity. CONSTITUTION: First format data is formed by sampling prescribed data from sampling data relating to one time of bus access, and stored in the memory for trace sequentially. A prescribed trigger condition is detected by monitoring the signal level of a prescribed signal relating to the bus access, and storage on the memory for trace is started or stopped by satisfying the trigger condition. Also, a FIFO buffer which stores the format data transiently is provided. and sampling-converted data is stored sequentially, and its write address is updated, and also, when the validity of stored data is defined by satisfying a filter condition, the write address at that time is stored, and the stored data up to the write address is autonomously read out, or when the invalidity of the stored data is defined by not satisfying the filter condition, an address stored in the write address is loaded.

7. 发明专利

JPH0367354A DECIDING SYSTEM FOR FINAL DATA CONTAINED IN TRANSFER DATA 失效
公开(公告)号：JPH0367354A
公开(公告)日：1991-03-22
申请号：JP20298089
申请日：1989-08-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： OKAZAKI MAKOTO , SHIBATA YUJI , KODA YOSHIFUMI , OKAMOTO HISASHI
IPC分类号： G06F13/38 , G06F13/36
摘要： PURPOSE:To decide the final data by providing a 2nd transfer queue memory address pointing register which shows an address where 1 is added to the contents of a 1st transfer queue memory address pointing register and compares the output of the 2nd transfer queue memory address pointing register with the output a transfer data memory. CONSTITUTION:The data groups D0... are successively transmitted from a memory 1 with an instruction of a transfer data memory address pointing register 3. Then a head address A0 and the next head address A3 of the data groups D0... stored in the memory 1 are transmitted with instructions of the transfer queue memory address pointing registers TOH 4 and 5. Then the address A3 shown by the TOH 5 is compared with the addresses A0, A1 and A3 of the data to be outputted from the memory 1 respectively. Then the address A2 obtained by subtracting 1 from the address A3 is compared with the addresses A0 - A3 of the memory 1. Thus the final data is decided when the coincidence is obtained from the comparison. In such a constitution, the final data contained in the transfer data can be decided without securing a memory area in a transfer queue memory 2 to show each entry data quantity despite the addition of the TOH 5.

8. 发明专利

JPH0367347A MEMORY TEST SYSTEM 失效
公开(公告)号：JPH0367347A
公开(公告)日：1991-03-22
申请号：JP20297889
申请日：1989-08-04
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： TEJIMA TORU , KODA YOSHIFUMI , HIRANO MASANORI , UEMORI AKIRA
IPC分类号： G06F12/08 , G06F12/16
摘要： PURPOSE:To continuously and efficiently test the memories by securing a constitution where a processor stores the head addresses of memories to extract them as the test data and counts up the address stored in a register by one step. CONSTITUTION:A processor 100 stores the head address of a memory 200 into an address register 300 and also stores the test data extracted out of the memory 200 into a register 400 respectively. Then the address of the register 300 is counted up by a step every time the test data stored in the register 400 is stored in the address stored in the register 300. At the same time, the test data is extracted out of the address stored in the register 300. Then the address is also counted up by a step every time the test data extracted from the register 300 is stored in the register 400. A count-up means 500 counts up the addresses of both registers 300 and 400, and these counted-up addresses are stored. As a result, the memories can be continuously and efficiently carried out.

9. 发明专利

JPS62272339A MEMORY CONTROL SYSTEM 失效
公开(公告)号：JPS62272339A
公开(公告)日：1987-11-26
申请号：JP11658686
申请日：1986-05-21
申请人： FUJITSU LTD , NIPPON TELEGRAPH & TELEPHONE
发明人： KODA YOSHIFUMI , KURAYA ETSUJI
IPC分类号： G06F12/16 , G06F12/06
摘要： PURPOSE:To prevent the reduction of access speed to a memory in a corresponding system and reduce the number of inter-system connection lines by providing both systems of a dual memory device with memory crossing parts and directly accessing the memory in the corresponding system and accessing the memory in the other system through memory crossing parts. CONSTITUTION:When a memory control part 2a writes data in a memory 1b, a memory crossing part 7a transfers an address (a) and data (d) from the memory control part 2a to a memory crossing part 7b. When receiving the address (a) and data (d), the memory crossing part 7b stores received data (d) in the memory 1b under the control of a memory control part 2b. When the memory control part 2a reads out data from the memory 1b, the memory crossing part 7a transfers the address (a) from the memory control part 2a to the memory crossing part 7b. The memory crossing part 7b reads out data (d) from the memory 1b and returns it to the memory crossing part 7a under the control of the memory control part 2b when receiving the address (a), and the memory crossing part 7a returns received data (d) to the memory control part 2a.

10. 发明专利

JPS6314556A CONTROL SYSTEM FOR MAINTENANCE 失效
公开(公告)号：JPS6314556A
公开(公告)日：1988-01-21
申请号：JP15916786
申请日：1986-07-07
申请人： FUJITSU LTD
发明人： KODA YOSHIFUMI
IPC分类号： G06F11/22 , H04M3/22 , H04M3/26
摘要： PURPOSE:To always exactly understand the state of a central control equipment by returning and reproducing the contents of a state display register of the central control equipment, in case the state display register of the central control equipment is varied from a testing device. CONSTITUTION:In formation which has laid down a key K of a testing device 2, and information of a bit corresponding to a key of a state display register 21 are compared by a variation detecting circuit 23, and its variation is detected. If the variation exists, the contents of the corresponding bit of a shift register 22 are set to a logical value '1', and all other bits are set to a logical value '0'. The contents of the register 22 are transferred in series to a shift register 13 of a central control equipment, allowed to take exclusive OR with the contents of a state display register and the register 13 by a changing circuit 12, and only the bit which is varied by the key K is varied. Also, the contents of the register 11 are transferred in series by the registers 13, 22 and recorded in the register 21. Accordingly, even if the equipment 1 rewrites other bit of the register 11, its state is displayed on the register 21, and a state of the equipment 1 can always be displayed exactly.

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