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1. 发明专利

JPH0383294A NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH0383294A
公开(公告)日：1991-04-09
申请号：JP21739189
申请日：1989-08-25
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SHOJI KAZUYOSHI , HAGIWARA TAKAAKI , NABEYA SHINJI , MUTO TADASHI , SAEKI SHUNICHI , KUBOTA YASURO , IZAWA KAZUTO , KAMIGAKI YOSHIAKI , MINAMI SHINICHI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06
摘要： PURPOSE:To prevent the deterioration of a characteristic in ROM owing to excessive writing by prohibiting the supply of a write voltage and the like after it is supplied to EPROM formed by means of dual gate transistors (TR) for prescribed time. CONSTITUTION:A timer TM provided in a timing control circuit CONT is started when a program signal, the inverse of PGM comes to L in a state where a write high voltage Vpp is impressed, a chip enable signal, the inverse of CE comes to L, an output enable signal, the inverse of OE to L. Then, the write voltage for the dual gate EPROM elements Q1-Q6 having control gates and floating gates whose write voltage is selected by setting an internal write signal, the inverse of We to be L when timer time elapses, is prohibited. It is the same for a deletion voltage, and the deterioration of the characteristic in the EPROM elements owing to the supply of the excessive voltage can be prevented.

2. 发明专利

JPH01294297A NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE 失效
公开(公告)号：JPH01294297A
公开(公告)日：1989-11-28
申请号：JP12546888
申请日：1988-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG , HITACHI DEVICE ENG
发明人： SHOJI KAZUYOSHI , HAGIWARA TAKAAKI , NABEYA SHINJI , MUTO TADASHI , SAEKI SHUNICHI , KUBOTA YASURO , IZAWA KAZUTO , KAMIGAKI YOSHIAKI , MINAMI SHINICHI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06
摘要： PURPOSE:To control the threshold voltage of a non-volatile storage element to be erased by monitoring the current flowing to this storage element to control a switch CONSTITUTION:A switch MOSFET Q17 which gives an erase voltage to a source line to which a non-volatile storage element Q1, which is provided with a control gate and a floating gate and has a stacked gate structure, is connected is so controlled that this switch is turned off at the time of detecting the current flowing to the non-volatile storage element Q1 to be erased. Thus, the electric characteristic of the non-volatile storage element is used and the change of its threshold voltage is monitored to prevent the excessive erase operation of the non-volatile storage element.

3. 发明专利

JPS6481058A SEMICONDUCTOR MEMORY DEVICE 失效
公开(公告)号：JPS6481058A
公开(公告)日：1989-03-27
申请号：JP23724187
申请日：1987-09-24
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： KUBOTA YASURO
IPC分类号： G06F12/14 , G06F21/24
摘要： PURPOSE:To surely prevent a foul access by adding a means to a comparison key data holding area to allow an access only when the data equal to the comparison key data set previously is supplied into a memory. CONSTITUTION:A comparator 8 compares sequentially the comparison key data CKED1-CKEDi read out of a comparison key data holding area ME2 with the key data KED1-KEDi supplied via a data input buffer 6 based on an extra high level supplied from an external address input terminals Ar1 and the column address signals supplied from external address input terminals AC1-ACn. These comparison results are stored in a shift register 9. Then a control means 10 allows an access to the corresponding data storing area only when the coincidence is obtained between the data CKED1-CKEDi and the data KED1-KEDi.

4. 发明专利

JPS6298668A CHARGE TRANSFER DEVICE 失效
公开(公告)号：JPS6298668A
公开(公告)日：1987-05-08
申请号：JP23741285
申请日：1985-10-25
申请人： HITACHI VLSI ENG , HITACHI LTD
发明人： FUSE YASUFUMI , KUBOTA YASURO , INOUE KIYOSHI
IPC分类号： H01L29/762 , H01L21/339 , H01L27/14 , H01L27/148 , H01L29/76 , H01L29/772 , H04N5/335 , H04N5/341 , H04N5/372
摘要： PURPOSE:To decrease the left amount of carriers to be transferred by delaying a drive signal transmitted over an electrode formed onto a pair of semiconductor regions, to which potential wells in different depth are shaped, on the semiconductor region side where the potential wells must be deepened by the voltage of the drive signal. CONSTITUTION:Delay means Del for transmitting drive signals phi1, phi2 over each storage electrode FG1-FG3 are shaped among respective storage electrode FG1-FG3 and signal lines L1 and L2, delaying the signals for a fixed time. The delay means Del increase the difference of the depth of a potential well in a low concentration region, in which carriers to be transferred are stored, and the depth of a potential well in a high concentration region adjacent in front of the low concentration region to the direction of transfer of carriers in the transition process of one transfer operation. Accordingly, the left amount of carriers to be transferred is decreased.

5. 发明专利

JPH1055684A SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH1055684A
公开(公告)日：1998-02-24
申请号：JP15034897
申请日：1997-05-23
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G11C16/02
摘要： PROBLEM TO BE SOLVED: To simplify a circuit and to stabilize erasing control of a memory cell by making voltage of a word line connected to a memory cell lower than voltage in a read-out mode, when verifying operation is performed in an erasing mode. SOLUTION: Prior to actual erasing operation, a series of pre-write operation is performed for all storage transistors, an initial setting for erasing operation is performed. An erasing pulse for erasing en bloc is generated and erasing operation is performed. After that, verifying operation is performed conforming to address setting. In verifying operation, reading operation is performed with operation voltage Vcv being lower than power source voltage Vcc of low voltage. At this point, power source voltage Vcc is applied to an internal circuit LOGC and a timing control circuit CNTR as operation voltage. When a storage transistor is made an on-state in this operation, its threshold voltage is recognized as an erasing state of Vcv, increment of an address counter circuit is performed and it is repeated until the last address.

6. 发明专利

JPH09231787A INFORMATION PROCESSING SYSTEM 失效
公开(公告)号：JPH09231787A
公开(公告)日：1997-09-05
申请号：JP1182097
申请日：1997-01-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G11C17/00 , G06F15/78 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To realize electrical erasing leaving a batch erasing type EEPROM as it is mounted on a system without lowering the throughput of the system by providing an erasing control circuit in the batch erasing type EEPROM. SOLUTION: An erasing control circuit (LOGC) conducts erasing operation to an electrical batch erasing type EEPROM shown in the figure according to an erasing instruction from the outside, and performs at least one-time read operation to a non-volatile storage element in memory arrays (M-ARY) carrying out erasing operation. The continuation and stoppage of erasing operation are controlled on the basis of the read information. Accordingly, since EEPROM itself has an automatic function with the read of erasing confirmation, control from a microprocessor is conducted for a slight time only for instruction for erasing start, and the burden on the microprocessor is lightened remarkably, and the throughput of the system is not sacrificed.

7. 发明专利

JPH09180488A SEMICONDUCTOR NONVOLATILE MEMORY DEVICE 失效
公开(公告)号：JPH09180488A
公开(公告)日：1997-07-11
申请号：JP1182197
申请日：1997-01-06
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SEKI KOICHI , WADA TAKESHI , MUTO TADASHI , KUBOTA YASURO , SHOJI KAZUYOSHI
IPC分类号： G11C17/00 , G11C16/02 , G11C16/06 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792
摘要： PROBLEM TO BE SOLVED: To obtain a semiconductor nonvolatile memory device by which the burden of a microprocessor is reduced by a method wherein, by the instruction of the microprocessor, an erase operation is performed automatically by an internal erase control circuit in a state that the circuit is separated from the microprocessor. SOLUTION: An N-channel MOSFET Q18 and a P-channel MOSFET Q17 which are switching-controlled by an erase circuit ERC are connected to a source line CS. The circuit ERC turns on the FET Q18 in a write mode and a readout mode, and it gives a ground potential to the source line CS. On the other hand, in an erase mode, the circuit ERC turns on the FET Q17, and it gives a high voltage VPP for erase to the source line CS. In this manner, the source line CS is installed as one line, the circuit ERC and the FET's Q17, Q18 are installed so as to correspond to it, and storage information in all memory cells constituting a memory array M-ARY can be erased collectively. Thereby, a control operation to an EEPROM from a microprocessor is performed in a slight time required for instructing the start of an erase operation, the burden of the microprocessor can be reduced, and the throughput of a system can be enhanced.

8. 发明专利

JPH1050077A NON VOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH1050077A
公开(公告)日：1998-02-20
申请号：JP12500497
申请日：1997-04-28
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHOJI KAZUYOSHI , MUTO TADASHI , KUBOTA YASURO , NABEYA SHINJI , SEKI KOICHI , IZAWA KAZUTO
IPC分类号： G11C16/02 , G11C16/06
摘要： PROBLEM TO BE SOLVED: To prevent the degradation of reliability caused by erasing operation by having a ramp rate gradually raising the potential of a source line to which a source of a non-volatile semiconductor memory element is coupled from low voltage to high volt age, when electric charges accumulated in a floating gate are extracted to a source side and erasing is performed. SOLUTION: Pulses CK, /CK are repeatedly generated, a potential V1 of a capacitor C4 is raised up gradually and in a staircase waveform state due to electric charges scattering, and the conductance of a MOSFET Q36 is gradually made high. And the conductance of a MOSFET Q17 is made gradually large in accordance with the gradation of a drain output V2 decided by a conductance ratio of the MOSFET Q36 and a MOSFET Q35, and erasing voltage supplied to a source line CS is made high in a ramp rate corresponding to voltage V1 of stairs waveform. By supplying these erasing voltage, the extraction of electric charges is started from the time when a point between a floating gate and a source of an erased storage element is made high voltage required for tunnel phenomenon.

9. 发明专利

JPH04362600A FUSE TRIMMING CIRCUIT AND SEMICONDUCTOR INTEGRATED CIRCUIT 失效
公开(公告)号：JPH04362600A
公开(公告)日：1992-12-15
申请号：JP16382891
申请日：1991-06-07
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： FUKUSHIMA MASANORI , KUBOTA YASURO , MATSUO AKINORI , KUROKOCHI SHINICHI , FURUSAWA KAZUNORI
IPC分类号： G11C17/00 , G11C29/00 , G11C29/04 , H01L21/82
摘要： PURPOSE:To prevent a floating node from generating in a stand-by state. CONSTITUTION:A fuse 12 is arranged between a P channel type MOSFET 11 whose gate electrode is fixed to a low potential side source Vss level and an N channel type MOSFET 13 controlled on/off by a chip enable signal CE, and a trimming output is attained from the P channel type MOSFET 11 side terminal of the fuse 12. Thus, in spite of the fusing/unfusing of the fuse 12, the logical condition of a node N2 is fixed to a high level in the stand-by state where the chip enable signal CE is negated to a low level and the generation of the floating node is prevented.

10. 发明专利

JPH0223597A NONVOLATILE SEMICONDUCTOR MEMORY 失效
公开(公告)号：JPH0223597A
公开(公告)日：1990-01-25
申请号：JP17223088
申请日：1988-07-11
申请人： HITACHI LTD , HITACHI VLSI ENG
发明人： SHOJI KAZUYOSHI , MUTO TADASHI , KUBOTA YASURO , NABEYA SHINJI , SEKI KOICHI , IZAWA KAZUTO
IPC分类号： G11C17/00 , G11C11/34 , G11C16/02 , G11C16/04 , G11C16/06
摘要： PURPOSE:To make partial erasure possible and, at the same time, to prevent the decline in reliability of the title device at the time of erasure by performing the erasure by applying a high voltage across a word and source lines and drawing out the electric charges accumulated in the floating gate of a memory cell to the source side. CONSTITUTION:When a P transistor (TR) Q17 for erasure is turned on and N TR Q18 for erasure is turned off through an erasure control circuit ERC 1, a high voltage is applied across a source line CS1 connected with the sources of memory TRs Q1-Q6 of a memory cell array M-ARY selected by word lines W1 and W2 connected with control gates. When the selectively applied high voltage is applied, a high voltage is generated across the word lines W1, W2 and source line CS1, because of the high voltage, electric charges accumulated in the floating gates are drawn out and partial erasure is performed on a selected memory cell TR only.

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