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1. 发明专利

JPH11196310A DIGITAL STILL CAMERA 失效
公开(公告)号：JPH11196310A
公开(公告)日：1999-07-21
申请号：JP36733597
申请日：1997-12-25
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI DEVICE ENG
发明人： INOOKA HIDEHIRO , SHUDO TAKASHI , KUWABARA TOKUYA , FURUHATA MAKOTO , OTAKA TERUAKI , YAMAUCHI KIYONARI , YANAGIYA TAKANOBU , TAKEYAMA HIROSHI
IPC分类号： H04N5/765 , H04N5/225 , H04N5/335 , H04N5/341 , H04N5/353 , H04N5/357 , H04N5/363 , H04N5/369 , H04N5/372 , H04N5/376 , H04N5/378 , H04N5/781
摘要： PROBLEM TO BE SOLVED: To obtain a camera that realizes efficient data processing with a simple configuration by forming a clock signal that is needed for a microprocessor based on an oscillation signal of a common reference frequency oscillator circuit and unifying a series of operations from image pickup to storage with the same oscillation signal. SOLUTION: In a CCD 3, photoelectric conversion elements are arranged in a matrix shape and the photoelectric conversion elements output light charge through a CCD for vertical transfer and a CCD for horizontal transfer time sequentially. The CCD 3 is designed for a digital still camera and reads out non-interlace mode. A drive circuit 2 forms a clock signal for transferring various signals which are necessary for the operation of the CCD 3 and a timing signal for sensitivity setting. The circuit 2 receives a timing signal from a programmable timer to a microcomputer 1 and a reference clock signal that is formed by a reference frequency oscillator circuit that is provided on the microcomputer 1.

2. 发明专利

JPH0799671A SIGNAL PROCESSING CIRCUIT FOR VTR 失效
公开(公告)号：JPH0799671A
公开(公告)日：1995-04-11
申请号：JP31898693
申请日：1993-11-24
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD , HITACHI MICOM SYST KK
发明人： FURUHATA MAKOTO , JIN TAKASHI , YAMAUCHI KIYONARI , ISHIHARA SHINICHI , YAMAZAKI KOICHI
IPC分类号： H04N9/80 , H04N9/793 , H04N9/83 , H04N9/84
摘要： PURPOSE:To provide a signal processing circuit for a VTR for making reproducing frequency conversion possible while eliminating color crosstalk and unnecessitating adjustment with simple constitution. CONSTITUTION:A first reproducing color under signal is delayed by a delay circuit 2 for one or two horizontal periods and the delayed second reproducing color under signal and the first reproducing color under signal are respectively frequency-converted to standard color signals by first and second frequency conversion circuits. The oscillation frequency signal of 2n {(n) is a natural number} of a carrier for the frequency conversion is frequency-divided so as to be a carrier frequency by a frequency divider circuit 12, four carriers respectively provided with the phases of 0 deg., 90 deg., 180 deg. and 270 deg. are formed and the carriers are selectively supplied to the first and second frequency conversion circuits 3 and 4 by switching circuits 13 and 14. The two frequency-converted signals are turned to the same phase or the opposite phase and subtracted or added and the color crosstalk between tracks is eliminated.

3. 发明专利

JPH08214329A METHOD AND CIRCUIT FOR DISCRIMINATING MODE FOR VTR 失效
公开(公告)号：JPH08214329A
公开(公告)日：1996-08-20
申请号：JP17818395
申请日：1995-06-21
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： FURUHATA MAKOTO , YAMAUCHI KIYONARI , JIN TAKASHI
IPC分类号： H04N9/80 , H04N9/84 , H04N9/873
摘要： PURPOSE: To provide a mode discriminating method and its discrimination circuit suitable for making into a semiconductor integrated circuit. CONSTITUTION: A signal in which a color under signal is delayed for two horizontal periods and the color under signal are added/subtracted by phase-shifting by +45 deg. and -45 deg., respectively, and it is discriminated whether a system is a PAL system or SECAM system by the change of calculated output at every horizontal period. Also, the color under signal supplied from an input terminal is delayed for two horizontal periods by a delay circuit 1, and the inputted color under signal and a delayed color under signal are added/subtracted by an arithmetic circuit 4 by phase-shifting by +45 deg. and -45 deg., respectively by phase circuits 2, 3, and the change at every horizontal period of the calculated output is detected by a signal detection circuit, then, it is discriminated whether the system is the PAL system or SECAM system. In this way, mode discrimination is performed by using the delay circuit 1 formed by a semiconductor integrated circuit, the phase circuits 2, 3 and the arithmetic circuit 4.

4. 发明专利

JPH09130237A PLL CIRCUIT AND TRANSFER DATA SIGNAL PROCESSOR 失效
公开(公告)号：JPH09130237A
公开(公告)日：1997-05-16
申请号：JP27909395
申请日：1995-10-26
申请人： HITACHI LTD , HITACHI MICROCOMPUTER SYST , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YAMAMOTO MOROHISA , FURUHATA MAKOTO , YAMAUCHI KIYONARI , JIN TAKASHI
IPC分类号： G06F1/12 , H03L7/087 , H03M1/12
摘要： PROBLEM TO BE SOLVED: To provide a PLL circuit capable of high-speed pull-in for the pull-in response of skewness and the pull-in response from a free-running oscillation state and to perform the A/D conversion processing of video signals and a character addition processing using it. SOLUTION: The output signals of a variable oscillator 101 oscillated by the frequency of N-fold of reference signals are frequency-divided to the frequency of L-fold (L

5. 发明专利

JPH10112042A OPTICAL INFORMATION REPRODUCING DEVICE 失效
公开(公告)号：JPH10112042A
公开(公告)日：1998-04-28
申请号：JP26405596
申请日：1996-10-04
申请人： HITACHI LTD
发明人： NISHIMURA KOICHIRO , NAKAJIMA JUNJI , TAKEUCHI TOSHIFUMI , HIROSE KOICHI , FURUHATA MAKOTO
IPC分类号： G11B7/09
摘要： PROBLEM TO BE SOLVED: To generate the tracking error signals which are idependent of the depths of the pits of a recording medium, have no offset and are generated by two phase correcting means of the device employing a phase difference system having a delaying means for the output of a quadripartite type light receiving cell. SOLUTION: Two pairs of the signals made by the pairs of the outputs of two cells arranged in the four diagonal locations of quadripartite type light receiving cells 18 are respectively inputted to circuit connection switching means 2 and 3 which are respectively controlled from the external. One of the outputs of the means 2 and 3 is inputted to adders 21 and 22 through delaying means 19 and 20 which are controlled from the external and the other output of the means 2 and 3 is directly inputted to the adders 21 and 22. The phase relationship of the two output signals are changed by the depths of the pits of the recording medium. Note that the means 2 and 3 are controlled so that the signals, whose phases are advanced, are inputted to the means 19 and 20. Thus, the phase difference in the two signals is resolved without depending on the depths of the pits, the phases of the signals of the adders 21 and 22 are made equal and the generation of the offset in the tracking error signals is prevented.

6. 发明专利

JPH09215004A COLOR SYSTEM DISCRIMINATION CIRCUIT 失效
公开(公告)号：JPH09215004A
公开(公告)日：1997-08-15
申请号：JP1629796
申请日：1996-02-01
申请人： HITACHI LTD
发明人： FURUHATA MAKOTO
IPC分类号： H04N9/80
摘要： PROBLEM TO BE SOLVED: To simply and surely discriminate the color system with a configuration suitable circuit integration independently of the stability of an APC loop by adding or subtracting a signal phase-shifted by +45 deg. and a signal phase- shifted by -45 deg.. SOLUTION: A delay circuit 1 delays a color under signal (a) by one horizontal period or two horizontal periods. A phase shift circuit 2 shifts a phase of the color under signal (a) before delay by -45 deg. (delayed phase) and a phase shift circuit 3 shifts a phase of the color under signal (a) after delay by +45 deg. (advanced phase). An arithmetic circuit 4 adds or subtracts the signal (d) shifted by +45 deg. and the signal (c) shifted by -45 deg.. The output e/f is used for a color system discrimination output to correctly identify whether the color under signal in a VTR is a signal of the NTSC system or the PAL-M system.

7. 发明专利

JPH08181605A PHASE CONTROL CIRCUIT 失效
公开(公告)号：JPH08181605A
公开(公告)日：1996-07-12
申请号：JP33737494
申请日：1994-12-26
申请人： HITACHI LTD , HITACHI VIDEO IND INF SYST INC , HITACHI MICROCOMPUTER SYST
发明人： SASAKI MASAHIRO , FURUHATA MAKOTO , YAMAMOTO MOROHISA
IPC分类号： H04N5/92 , H03B5/32 , H03L7/099
摘要： PURPOSE: To make phase control stable by giving an output of a variable adder circuit whose plural input terminals receive an output signal of a subtractor circuit or an amplitude reduction circuit to an amplifier circuit so as to eliminate harmonics of an oscillating frequency. CONSTITUTION: One and other terminals of a resonance circuit RES1 provided to an external part are connected respectively to external terminals T0 , T1 and an input terminal of a band limit circuit BWC1 is substantially coupled with the terminals T0 , T1 . The phase control circuit is provided with a phase shift circuit PTR1 whose input terminal receives an output signal of the circuit BWC1, an amplitude reduction circuit ADC1, a subtractor circuit SUB1, a variable adder circuit VAD1, and an amplifier circuit AMP1. An output signal of the circuit PTR1 is given to an inverting input terminal (-) of the circuit SUB 1 and an output signal of the circuit ADC1 is given to its noninverting terminal (+). Furthermore, respective terminals of the circuit VAD1 receive outputs from the circuits SUB1, ADC1 and the result of the sum is given to the circuit AMP coupled with the terminals T0 , T1 . After the signal is amplified in the circuit AMP, from which the amplified signal is fed to a circuit RES1.

8. 发明专利

JPH02297671A METHOD FOR SUPPORTING SYSTEM DESIGN BY CONTINUOUS SIMULATION LANGUAGE 失效
公开(公告)号：JPH02297671A
公开(公告)日：1990-12-10
申请号：JP11730989
申请日：1989-05-12
申请人： HITACHI LTD
发明人： HAYASHI SHINICHI , WATANABE TOSHINORI , FURUHATA MAKOTO
IPC分类号： G01R31/28 , G06F17/50
摘要： PURPOSE:To easily execute simulation by constituting a model for a function level and a circuit level by using continuous simulation language, controlling time and accuracy for calculation and executing the simulation. CONSTITUTION:The function / circuit mixing model is formed by the continuous simulation language. Namely, when a system, in which analog and digital circuits are mixed, is formed to be the model, the analog circuit is described by Kirchhoff's law and the digital circuit is described by a transfer function. When the system, in which the function level and circuit level are mixed, is formed to be the model, the function level is described by the transfer function and the circuit level is described by the Kirchhoff's law or a Boolean expression. In the case of a stiff system, namely, when a high-speed part and a low-speed part are mixed, the high-speed part is described by a frequency and phase and the low-speed part is described by a voltage and current. Thus, the simula tion can be easily executed.

9. 发明专利

JPS61208588A ELECTRONIC DEVICE 失效
公开(公告)号：JPS61208588A
公开(公告)日：1986-09-16
申请号：JP4969485
申请日：1985-03-13
申请人： HITACHI LTD
发明人： OKADA YUTAKA , WASHIO KATSUYOSHI , WATABE TOMOYUKI , OGURA SADAO , OKABE TAKAHIRO , FURUHATA MAKOTO , HORIE NOBORU
IPC分类号： G06K19/07 , B42D15/10 , G06F15/02 , G06K7/00 , G07C9/00
摘要： PURPOSE:To require no insertion to a card reader and the like and control a device to be controlled without contact by transmitting an information signal by an electronic circuit incorporated in a small object and transmitting the information without contacting another device. CONSTITUTION:In an electronic device 11, an input key 12, an encoder 13, an FM modulator 14 are incorporated. By operating the input key and inputting a number, this number is stored in the encoder 13. An internal information of the encoder 13 is fed to the FM modulator 14 and a modulated output is fed out to an air through an antenna. This signal is received by a device 15 to be controlled. The signal inputted to an FM demodulator 16 from the antenna of the device 15 to be controlled is demodulated herein and passes through a decoder and a discriminator 17. At this time, only when the signal coincides with the content of the discriminator 17, a driver 18 operates to control a key 19.

10. 发明专利

JPS61137424A Digital input interface circuit 失效
标题翻译：数字输入接口电路
公开(公告)号：JPS61137424A
公开(公告)日：1986-06-25
申请号：JP25915684
申请日：1984-12-10
申请人： Hitachi Ltd
发明人： FURUHATA MAKOTO
IPC分类号： H03K19/018
摘要： PURPOSE: To input an external signal to a digital circuit at a high speed with simple circuit constitution by operating a bipolar transistor (TR) which converts the level of the external signal to the input threshold value of the digital circuit while its base is grounded.
CONSTITUTION: A signal source Sg outputs a signal whose amplitude corresponds to the level of a current, i.e. current signal. Consequently, the PNP bipolar TRQp operates on common base basis to convert the input signal from the signal source Sg to the input threshold value (about 0∼0.7V) of the IIL. The cutoff frequency fα of the common base TR is much higher than the cutoff frequency fβ of a common emitter TR and the considerably high cutoff frequency fα is obtained even by the PNP bipolar TR. Consequently, the maximum frequency of a signal which can be inputted to the IIL is increased greatly as compared with the conventional frequency.
COPYRIGHT: (C)1986,JPO&Japio
摘要翻译：目的：通过操作双极晶体管（TR），通过简单的电路结构将数字电路输入外部信号到数字电路，双极晶体管（TR）将外部信号的电平转换为数字电路的基极接地时的输入阈值。构成：信号源Sg输出其幅度对应于电流的电平即电流信号的信号。因此，PNP双极性TRQp基于共同基础工作，将来自信号源Sg的输入信号转换成IIL的输入阈值（约0-0.7V）。公共基极TR的截止频率fal远高于公共发射极TR的截止频率fbeta，甚至通过PNP双极性TR获得相当高的截止频率falpha。因此，与常规频率相比，可以输入到IIL的信号的最大频率大大增加。

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