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1. 发明专利

JPH11316752A MICRO COMPUTER 失效
公开(公告)号：JPH11316752A
公开(公告)日：1999-11-16
申请号：JP6778199
申请日：1999-03-15
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO NARIHISA , TERASAWA MASAAKI
IPC分类号： G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a micro computer incorporating a flash memory whose operability is satisfactory. SOLUTION: A flash memory FMRY has large memory blocks LMB and small memory blocks SMB, whose storage capacities differ as a collective deletion possible unit. At the time of tuning control data, etc., which the flash memory holds, holding information of the flash memory can be changed on a real time basis in synchronizing with the control operation of the micro computer. In such a case, the area of the specified address of incorporated RAM is changed and arranged so that it is overlapped with the address of a memory block whose storage capacity is smaller than that of incorporated RAM. Work is executed in the specified address of RAM, the arrangement address of RAM is restored to an original state and the content of the memory block is rewritten by information of the specified address of RAM.

2. 发明专利

JPH11288410A MICROCOMPUTER 失效
公开(公告)号：JPH11288410A
公开(公告)日：1999-10-19
申请号：JP33047398
申请日：1998-11-20
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO NARIHISA , TERASAWA MASAAKI
IPC分类号： G11C16/06 , G06F9/06 , G06F11/00 , G06F11/22 , G06F12/00 , G06F12/06 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer incorporating a convenient flash memory. SOLUTION: This microcomputer is provided with an input terminal Pmode of an operation mode signal MODE for selectively designating a first operation mode for allowing an incorporated central processing unit CPU to control rewriting to an electrically erasable and writable non-volatile flash memory FMRY, and a second operation mode for allowing an outside PROM writer to control the rewriting. The flash memory FMRY is provided with a large memory block LMB and a small memory block SMB whose storage capacities are made different as end batch erasable units. The small memory block has at most the storage capacity of a RAM. Those memory blocks LMB and SMB are used according to information amounts to be stored.

3. 发明专利

JP2002304894A MANUFACTURING METHOD FOR PRINTED CIRCUIT BOARD 审中-公开
公开(公告)号：JP2002304894A
公开(公告)日：2002-10-18
申请号：JP2002031610
申请日：2002-02-08
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO NARIHISA , TERASAWA MASAAKI
IPC分类号： G11C17/00 , G06F11/00 , G06F15/78 , G11C16/02
摘要： PROBLEM TO BE SOLVED: To provide a manufacturing method for a printed circuit board in which a flash memory being easy to use is mounted. SOLUTION: A CPU is a central processing unit, a FMRY is a non-volatile flash memory being erasable and writable. A resin sealing type microcomputer having a first operation mode in which an incorporated central processing unit(CPU) controls rewriting for this flash memory (FMRY) and a second operation mode in which an external PROM writer controls the flash memory is provided, a program is written in the flash memory (FMRY) in the second operation mode, the computer for which writing is performed is mounted on a printed circuit board, after that, rewriting of a program held by the flash memory (FMRY) is performed in the first operation mode.

4. 发明专利

JPH11316753A MICRO COMPUTER 失效
公开(公告)号：JPH11316753A
公开(公告)日：1999-11-16
申请号：JP6778099
申请日：1999-03-15
申请人： HITACHI LTD , HITACHI ULSI SYS CO LTD
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO NARIHISA , TERASAWA MASAAKI
IPC分类号： G11C16/04 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a micro computer incorporating a flash memory whose operability is satisfactory. SOLUTION: A flash memory FMRY has a plurality of memory arrays where a plurality of memory cells are matrix-arranged. Respective bit data of data constituted of a plurality of bits are divided and are stored in the memory arrays. Respective pieces of bit data stored in the memory arrays are outputted in accordance with the access of a central processing unit CPU via an address bus. The data is constituted of bit data and data are outputted to the central processing unit CPU via a data bus.

5. 发明专利

JP2003288791A Semiconductor integrated circuit device and microprocessor 审中-公开
标题翻译：半导体集成电路设备和微处理器
公开(公告)号：JP2003288791A
公开(公告)日：2003-10-10
申请号：JP2003048678
申请日：2003-02-26
申请人： Hitachi Ltd , 株式会社日立製作所
发明人： ISHIKAWA EIICHI , SAITO YASUYUKI , SATO NARIHISA , YADA NAOKI , MATSUBARA KIYOSHI
IPC分类号： G11C16/06 , G06F15/78 , G11C16/02 , G11C16/04 , G11C29/00 , G11C29/56
摘要： PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device capable of solving a restriction that an object once programmed cannot be changed later such as a laser fuse. SOLUTION: The device has a nonvolatile memory area (300) which is electrically erasable and writable and stores adjustment information, memory circuits (TRMR1, TRMR2) which is combined with the nonvolatile memory area so as to receive the adjustment information and stores the adjustment information, and an internal circuit (42) combined with the memory circuit. The adjustment information is transferred to the memory circuit from a nonvolatile memory element responding to the initialization operation of the semiconductor integrated circuit device, and the operation of the internal circuit is controlled by the adjustment information stored in the memory circuit. Thereby, trimming can be freely made by software. COPYRIGHT: (C)2004,JPO
摘要翻译：要解决的问题：提供一种半导体集成电路器件，其能够解决一旦被编程的对象稍后不能改变的限制，例如激光熔丝。解决方案：该装置具有电可擦除和可写入的非易失性存储区域（300），并存储调整信息，与非易失性存储区域结合的存储电路（TRMR1，TRMR2），以便接收调整信息并存储所述调整信息以及与所述存储器电路组合的内部电路（42）。响应于半导体集成电路装置的初始化操作，调整信息从非易失性存储元件转移到存储器电路，内部电路的操作由存储在存储电路中的调整信息控制。因此，可以通过软件自由地进行修剪。版权所有（C）2004，JPO

6. 发明专利

JP2003203064A MICROCOMPUTER 审中-公开
公开(公告)号：JP2003203064A
公开(公告)日：2003-07-18
申请号：JP2003023225
申请日：2003-01-31
申请人： HITACHI LTD
发明人： MATSUBARA KIYOSHI , SATO NARIHISA , MUKAI HIROFUMI , ISHIKAWA EIICHI
IPC分类号： G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer capable of rewriting a built-in flash memory by utilizing a generally used PROM writer. SOLUTION: This microcomputer 1 is provided with a central processor 10 and the electrically writable flash memory FMRY2 on one semiconductor base, and has a first operation mode operated in accordance with the command inputted from an external device 30. When a read command for reading out the information stored in the flash memory from the external device is inputted to the microcomputer in the first operation mode, the central processor is separated from a bus. Whereby the external device can freely read large volumes of flash memory built in the microcomputer on the basis of the read command in accordance with its specification. COPYRIGHT: (C)2003,JPO

7. 发明专利

JP2003076672A Microcomputer 审中-公开
标题翻译： MICROCOMPUTER
公开(公告)号：JP2003076672A
公开(公告)日：2003-03-14
申请号：JP2002240385
申请日：2002-08-21
申请人： Hitachi Ltd , Hitachi Ulsi Systems Co Ltd , 株式会社日立製作所 , 株式会社日立超エル・エス・アイ・システムズ
发明人： MATSUBARA KIYOSHI , YASHIKI NAOKI , BABA SHIRO , ITO TAKASHI , MUKAI HIROFUMI , SATO NARIHISA , TERASAWA MASAAKI
IPC分类号： G06F12/06 , G06F11/00 , G06F12/00 , G06F15/78
摘要： PROBLEM TO BE SOLVED: To provide a microcomputer satisfactory in use convenience and incorporating a flash memory therein. SOLUTION: This microcomputer having a central processing unit, the flash memory, mask ROM, serial communication interface, and an I/O port has a first function for writing program into the flash memory by PROM writer before the microcomputer sealed by resin is mounted in a system and a second function for rewriting program region of the flash memory by executing rewrite control program stored in the mask ROM by the central processing unit while the microcomputer is mounted in the system. In the second function, the program region of the flash memory is rewritten by the information inputted from the outside through the serial communication interface and the I/O port.
摘要翻译：要解决的问题：提供令人满意的使用便利性并在其中并入闪存的微型计算机。解决方案：具有中央处理单元，闪速存储器，掩模ROM，串行通信接口和I / O端口的微型计算机具有在由树脂封装的微型计算机安装在PROM写入器之前将程序写入闪速存储器的第一功能用于通过在微型计算机安装在系统中的同时通过中央处理单元执行存储在掩模ROM中的重写控制程序来重写闪速存储器的程序区域的系统和第二功能。在第二功能中，通过串行通信接口和I / O端口从外部输入的信息来改写闪速存储器的程序区域。

8. 发明专利

JP2002032996A MICROCOMPUTER SYSTEM 失效
公开(公告)号：JP2002032996A
公开(公告)日：2002-01-31
申请号：JP2001167630
申请日：2001-06-04
申请人： HITACHI LTD
发明人： MATSUBARA KIYOSHI , SATO NARIHISA , ISHIKAWA EIICHI
IPC分类号： G06F12/16 , G06F15/78 , G11C29/00 , G11C29/04
摘要： PROBLEM TO BE SOLVED: To provide a system which can relieve a defect of a non-volatile storage device on-chipped to a microcomputer on board. SOLUTION: A non-volatile storage device on-chipped to a microcomputer is provided with memory cells (MC-R) for redundancy and memory cells (MC-C) for storing relieving information specifying memory cells (MC) to be substituted by a memory cell for redundancy. At the time of write-in of relieving information, selection of the memory cells (MC-C) is performed by a relieving bit selecting circuit (RSEL). The written relieving information is initially loaded to a relieving information latch (CLAT) by indication of a reset signal (MD2). An address comparing compares relieving information with address information from the compares relieving information with address information from the circuit (ACMP) compares relieving information with address information from the outside, when they are coincident, a memory cell (MC-R) for redundancy is selected. A system reset signal (22) utilized for generation of a reset signal (MD2) is outputted to a microcomputer by an another circuit (23).

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