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1. 发明专利

JP2000201036A HIGH FREQUENCY AMPLIFIER CIRCUIT DEVICE 失效
公开(公告)号：JP2000201036A
公开(公告)日：2000-07-18
申请号：JP123999
申请日：1999-01-06
申请人： HITACHI LTD , HITACHI TOBU SEMICONDUCTOR LTD
发明人： YASUDA TAKESHI , MASUDA AKIRA
IPC分类号： H01L27/06 , H01L21/8234 , H01L29/80 , H03F3/193 , H03F3/195 , H03G3/10
摘要： PROBLEM TO BE SOLVED: To decrease the gate voltage of a control transistor in proportion to an AGC potential, and to reduce a voltage by providing a prescribed circuit constitution by using dual FET for both a main transistor and the transistor for controlling a gain. SOLUTION: A common part 21 of transistors TC1 and TC2 of a control transistor Q2 in a dual gate structure is connected through a resistor R2 with a gate G1 of a main body transistor Q1, and a gate G2 of the main transistor Q1 is connected with a gate 1 of the control transistor Q2. When an AGC potential is impressed to the gate G2, the voltage of the gate G1 of the control transistor Q2 is decreased according as the AGC potential is decreased, and currents running through the control transistor Q2 are decreased, and a potential VC of the common part 21 is increased according to the decrease of a voltage. As a result, a voltage is supplied to the gate G1 of the main transistor Q1 so that the function of a forward AGC function can be obtained. Thus, the voltage of the gate 1 of the control transistor is decreased in proportion to the decrease of the AGC potential so that distortion characteristics at the time of attenuating a gain can be improved.

2. 发明专利

JPS641261A ELECTRONIC DEVICE 失效
公开(公告)号：JPS641261A
公开(公告)日：1989-01-05
申请号：JP15546087
申请日：1987-06-24
申请人： HITACHI LTD
发明人： MASUDA AKIRA
IPC分类号： H01L23/28 , H01L23/40
摘要： PURPOSE:To obtain insulation while a decrease in a heat sink is avoided by forming a large diameter section in a header mounting hole when an electronic device is secured to a heat sink plate, and partly thickly forming the periphery of the hole of an insulating plate. CONSTITUTION:A resin-insulated power transistor 1 is disposed at a predetermined position of a heat sink plate 14 to bring an insulating plate 12 into contact with its surface with a header 5 directed toward the plate 14. Then, a clamper, such as a self-tapping screw member 16 is inserted from above a package 10 into a mounting hole 13, and engaged within a clamping hole 15 to be clamped on the plate 14. In this case, a tapered large-diameter section 9 is formed in the mounting hole 8 of the header 5. Thus, since an insulating plate 12 around the hole 13 is partly thickly formed, even if chips 17 generated upon engaging of the member 16 within the hole 15 are intruded to the periphery of the hole 13, an insulating gap between the chips and the surface of the header can be sufficiently obtained. As a result, it can prevent the insulation of a transistor from decreasing.

3. 发明专利

JPS6245204A COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPS6245204A
公开(公告)日：1987-02-27
申请号：JP18416185
申请日：1985-08-23
申请人： HITACHI LTD
发明人： MASUDA AKIRA
IPC分类号： H03G3/00 , H03F3/34 , H03F3/345 , H03G3/30 , H04B1/04
摘要： PURPOSE:To decrease the deviation of the frequency characteristic and to apply stable power control by using an enhancement and a depletion MOSFET connected in multi-stage forming an amplifier. CONSTITUTION:Plural amplifiers forming a power control circuit are formed by enhancement MOSFETs and depletion MOSFETs. In applying gain control by supplying in common a control voltage for gain control, the position of change in an input gate capacitance is deviated. Then the deviation in the frequency characteristic is reduced and stable power control is applied.

4. 发明专利

JPS54128274A RESINNSEALED SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS54128274A
公开(公告)日：1979-10-04
申请号：JP3550978
申请日：1978-03-29
申请人： HITACHI LTD
发明人： MASUDA AKIRA , TAIRA YASUO
IPC分类号： H01L23/48 , H01L23/28
摘要： PURPOSE:To reduce the feedback capacity for the device to be used suitably at the high frequency region by forming the tip of the lead for earth into a disk shape with the semiconductor pellet provided at the center of the disk and then covering the pellet and the tips of plural leads of the pellet. CONSTITUTION:Tip A of lead 2a for source S is formed into a disk, and semiconductor pellet 3 is attached at the center of disk part A. Then lead 2b for drain D, lead 2c for 2nd gate G2 and lead 2d for 1st gate G1 are provided in three directions centering on pellet 3, and mold part 1 is formed covering over the tip parts of these leads as well as pellet 3. Here, the contact area is increased between part 1 and lead 2a for the source to be earthed, and the feedback capacity is reduced. Thus, the device can be used suitably at the high frequency region.

5. 发明专利

JPH05152978A HIGH FREQUENCY POWER AMPLIFIER CIRCUIT 失效
公开(公告)号：JPH05152978A
公开(公告)日：1993-06-18
申请号：JP20489791
申请日：1991-07-19
申请人： HITACHI LTD
发明人： MASUDA AKIRA , YAMADA SHINJI , ITO MAMORU
IPC分类号： H03F3/195 , H03F3/60 , H04B1/04
摘要： PURPOSE:To keep a satisfactory amplification characteristic and power efficiency by constituting the high frequency power amplifier circuit of a post-stage circuit and a pre-stage driving circuit, and constituting an amplifier of the post-stage circuit, and an amplifier of the pre-stage circuit, of a GaAsFET and an enhancement type SiMOS transistor, respectively. CONSTITUTION:Outputs of driving circuits 102, 103 of a power amplifier circuit 100 can be subjected to variable control by a positive bias voltage +VG applied to the respective gates of enhancement type SiMOSFETs M1, M2. By output control of these circuits 102, 103, the whole power gain of the high frequency power amplifier circuit 100 can be subjected to variable control, in a state that an operating condition of a post-stage circuit 101 is held in an optimal state. On the other hand, since the driving circuits 101, 103 are SiMOSFETs, the power efficiency becomes lower in a frequency band, for instance, of >=1GHz, compared with the post-stage circuit 101 of a GaAsFET, but the influence exerted on the power efficiency of the whole circuit is small. Accordingly, while keeping high power efficiency with a simple power source and circuit configuration, high frequency output power can be subjected to variable control in a wide range.

6. 发明专利

JPH04122129A MOBILE RADIO COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPH04122129A
公开(公告)日：1992-04-22
申请号：JP24311990
申请日：1990-09-13
申请人： HITACHI LTD
发明人： YAMADA SHINJI , MASUDA AKIRA
IPC分类号： H03G3/20 , H04B1/04 , H04B1/3822 , H04B1/40 , H04B7/26 , H04W52/00
摘要： PURPOSE:To improve the stability of transmission operation, low power consumption, low cost and space saving performance by using a clock signal in a control unit as an input power supply so as to give a bias voltage of an opposite polarity to a high frequency power amplifier circuit. CONSTITUTION:Since a negative voltage is generated by using a clock signal CLK of a prescribed period as an input power supply, a negative bias voltage -VB with high stability and high precision is given to a GaAsFET 20 of a high frequency power circuit. Thus, the transmission is surely made stable. Moreover, power consumption and circuit cost required to obtain the negative bias voltage -VB are respectively reduced by using the clock signal CLK for the input power supply of a negative voltage generating circuit 26. Furthermore, since the negative voltage generating circuit 26 to obtain the negative bias voltage -VB is provided in a separate control unit 7 from a transmission unit 2, the efficiency of mount and the degree of freedom of the design of the external shape are ensured.

7. 发明专利

JPH0395940A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPH0395940A
公开(公告)日：1991-04-22
申请号：JP23356889
申请日：1989-09-07
申请人： HITACHI LTD
发明人： SHIGENO YASUSHI , MASUDA AKIRA , SAKAMOTO KAZUMICHI
IPC分类号： H01L29/812 , H01L21/338
摘要： PURPOSE:To alleviate variation in a gain for variation in a voltage between a gate and a source by shortening the width of the gate as compared with the width of the source or drain in a field effect transistor(FET) so that a current flows even in a state that a voltage is not applied. CONSTITUTION:A structure in which a source electrode 3, a gate electrode 4 and a drain electrode 5 are aligned on an active layer 2 of a main surface of a semi-insulating GaAs substrate 1 is provided, and the width Wq of a gate is shortened by about l as compared with the width Ws of a source and the width Wd of a drain of the same length. In such a FET, when a potential is applied between the electrodes 5 and 3, a current flows to the layer 2 between both the electrodes. When a voltage is applied between the electrodes 4 and 3, the current flowing to the electrodes 5, 3 is varied. Even if a voltage is not applied between the gate and the source, a current flows in a region in which the electrode 4 is not provided between the electrodes 3 and 5 to alleviate a variation in a gain.

8. 发明专利

JPS62120130A COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPS62120130A
公开(公告)日：1987-06-01
申请号：JP25850185
申请日：1985-11-20
申请人： HITACHI LTD
发明人： MASUDA AKIRA
IPC分类号： H04B1/04
摘要： PURPOSE:To reduce the deviation of an output power of a high frequency signal by constituting plural amplification stages employed to a power control circuit of a power MOSFET, varying the gate voltage of the 1st stage power MOSFET to shift the changing points of the gate-source capacitance of the both. CONSTITUTION:A comparator 31 obtains a comparison output Vb between a signal V and an output signal Va. The output Vb, that is, a voltage at a point X changes corresponding to the electric field strength, then a gate voltage Vgs of a power MOSFET Q1 changes depending on the electric field strength and the gain control of the 1st stage amplifier is applied. The gate-source capacitance Ciss of the FET Q1 is constant. Thus, in setting a voltage V1 to a voltage level deviated from the range of the change in the comparison output Vb, the coincidence of the changing points of both the Ciss is prevented. As a result, the entire capacitance change of a power control circuit 14 is not increased and the power control is stabilized.

9. 发明专利

JPS6253009A COMMUNICATION EQUIPMENT 失效
公开(公告)号：JPS6253009A
公开(公告)日：1987-03-07
申请号：JP19191585
申请日：1985-09-02
申请人： HITACHI LTD
发明人： MASUDA AKIRA
IPC分类号： H03G3/00 , H03G3/10 , H03G3/20 , H03G3/30 , H04B1/04
摘要： PURPOSE:To reduce the deviation of an output power of a high frequency signal by applying individually a control voltage to plural amplifiers and varying the control voltage fed to the 1st stage amplifier. CONSTITUTION:A power control circuit 14 uses a signal V corresponding to an electric field strength to control an output voltage. The bias voltage of a power MOSFET Q1 being the 1st stage amplifier of the power control circuit 14 changes corresponding to the electric field strength and a bias voltage of a power MOSFET Q2 being the 2nd stage amplifier is fixed by a voltage V1. Thus, in setting the voltage V1 to a voltage level shifted from the changing range of an output VB of a comparator 31,the coincidence of the change in a gate-source capacitance of the FETs Q1, Q2 is prevented. Thus, the capacitance change in the entire power control circuit 14 is reduced to decrease the deviation of the output power of the high frequency signal.

10. 发明专利

JPS60177723A OUTPUT CIRCUIT 失效
公开(公告)号：JPS60177723A
公开(公告)日：1985-09-11
申请号：JP3235784
申请日：1984-02-24
申请人： HITACHI LTD
发明人： URAGAMI KEN , SUZUKI YUKIROU , KATOUNO SHINJI , IWAMURA MASAHIRO , MASUDA AKIRA , YAMAUCHI TATSUMI
IPC分类号： H03K19/0175 , H03K17/04 , H03K17/60 , H03K19/0944
摘要： PURPOSE:To reduce considerably the power consumption which is needed to keep and output in an inactive state having a high impedance, by setting a switching element in series to a working power supply path of a circuit set at a preceding stage for drive of an output stage and at the same time controlling said switching element with an enable signal. CONSTITUTION:When the logic state of an enable signal EN is set at ''H'' at the output side of an enable control circuit 30 a p channel MOS field effect transistor TRM3 set in series to a power supply path is kept on (conductive state) to supply a working current to a circuit of the preceding stage. When the logic state of the signal EN is changed to ''L'', the TRM3 is turned off to cut off the working currents of TRM1 and M2 respectively. Thus no base current is supplied to both TRQ1 and Q2 of an output stage. Thus both TRQ1 and Q2 are turned off and an output OUT is put under a floating state, i.e., an inactive stage of a high impedance regardless of the logic state of an input IN.

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