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1. 发明公开

EP1139302A4 METHOD OF CHECKING AUTHENTICITY OF SHEET WITH BUILT-IN ELECTRONIC CIRCUIT CHIP 审中-公开
标题翻译：方法进行验证，通过内置的电路芯片提供的片材的制备
公开(公告)号：EP1139302A4
公开(公告)日：2005-07-27
申请号：EP99973338
申请日：1999-12-03
申请人： HITACHI LTD , HITACHI RES INST
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G07D7/00 , G07D7/04 , G07D7/12 , G07D7/06 , B42D15/10 , G06K19/073
CPC分类号： G06Q20/042 , G07D7/003 , G07D7/0047 , G07D7/01 , G07D7/12 , G07D7/2033
摘要： A method of checking the authenticity of a sheet having visible information on it and including a built-in electronic circuit chip that information can be read from and written to. The method comprises the steps of encrypting the visible information on the sheet and storing it in the electric circuit chip, and comparing the visible information on the sheet with the information stored in the electric circuit chip to check the authenticity.

2. 发明申请

WO0033249A9 METHOD FOR MOUNTING ELECTRONIC CIRCUIT CHIP 审中-公开
标题翻译：安装电子线路芯片的方法
公开(公告)号：WO0033249A9
公开(公告)日：2001-03-15
申请号：PCT/JP9906595
申请日：1999-11-26
申请人： HITACHI LTD , OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G06K19/077 , B42D15/10
CPC分类号： G06K19/07747 , G06K19/07718 , G06K19/07745 , G06K19/07749 , H01L2924/0002 , H01L2924/3511 , Y10T29/49018 , H01L2924/00
摘要： A method for mounting a platelike electronic circuit chip together with another platelike electronic device on a flexible sheet, characterized in that the electronic circuit chip and the other electronic device are so selected that the plate face of the other electronic device is larger than that of the electronic circuit chip, the plate face of the other electronic device and that of the electronic circuit chip are parallel to the sheet, and the plate face of the electronic circuit chip lies within the plate face of the other electronic device when viewed vertically to the sheet.
摘要翻译：一种用于将片状电子电路芯片与另一片状电子器件一起安装在柔性片上的方法，其特征在于，电子电路芯片和另一电子器件被选择为使得另一电子器件的板面大于电子电路芯片，其他电子装置的板面和电子电路芯片的板面平行于片材，并且当垂直于片材垂直观察时，电子电路芯片的板面位于另一电子装置的板面内。

3. 发明专利

DE69941548D1 未知
公开(公告)号：DE69941548D1
公开(公告)日：2009-11-26
申请号：DE69941548
申请日：1999-11-26
申请人： HITACHI LTD
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G06K19/077 , B42D15/10
摘要： In a method of mounting a planar electronic circuit chip (1) onto a flexible sheet (200) together with another planar electronic element (2,3), the electronic circuit part and the other electric element are selected so that the planar surface of the other electric element is greater than the planar surface of the electronic circuit chip, and the other electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the other electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.

4. 发明专利

DE69934715T2 未知
公开(公告)号：DE69934715T2
公开(公告)日：2007-10-18
申请号：DE69934715
申请日：1999-11-26
申请人： HITACHI LTD
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G06K19/077 , B42D15/10
摘要： In a method of mounting a planar electronic circuit chip (1) onto a flexible sheet (200) together with another planar electronic element (2,3), the electronic circuit part and the other electric element are selected so that the planar surface of the other electric element is greater than the planar surface of the electronic circuit chip, and the other electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the other electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.

5. 发明专利

DE69934715D1 未知
公开(公告)号：DE69934715D1
公开(公告)日：2007-02-15
申请号：DE69934715
申请日：1999-11-26
申请人： HITACHI LTD
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G06K19/077 , B42D15/10
摘要： In a method of mounting a planar electronic circuit chip (1) onto a flexible sheet (200) together with another planar electronic element (2,3), the electronic circuit part and the other electric element are selected so that the planar surface of the other electric element is greater than the planar surface of the electronic circuit chip, and the other electric element and the electronic circuit chip are mounted on the sheet so that the planar surface of the other electric element and the planar surface of the electronic circuit chip are in parallel with the sheet surface, and the planer surface of the electronic circuit chip is accommodated within the planar surface of the another electric element as viewed in a direction perpendicular to the sheet surface.

6. 发明公开

EP1136945A4 METHOD FOR MOUNTING ELECTRONIC CIRCUIT CHIP 有权
标题翻译：方法安装一个电路
公开(公告)号：EP1136945A4
公开(公告)日：2003-07-16
申请号：EP99973144
申请日：1999-11-26
申请人： HITACHI LTD
发明人： OKAMOTO CHIKASHI , TAKARAGI KAZUO , TSUJI KAZUTAKA , USAMI MITSUO , YASUNOBU CHIZUKO , ISOBE ASAHIKO , TSUNEMI YASUHIRO , YAGI HIROYUKI
IPC分类号： G06K19/077 , B42D15/10
CPC分类号： G06K19/07747 , G06K19/07718 , G06K19/07745 , G06K19/07749 , H01L2924/0002 , H01L2924/3511 , Y10T29/49018 , H01L2924/00
摘要： A method for mounting a platelike electronic circuit chip together with another platelike electronic device on a flexible sheet, characterized in that the electronic circuit chip and the other electronic device are so selected that the plate face of the other electronic device is larger than that of the electronic circuit chip, the plate face of the other electronic device and that of the electronic circuit chip are parallel to the sheet, and the plate face of the electronic circuit chip lies within the plate face of the other electronic device when viewed vertically to the sheet.

7. 发明专利

JPS63279199A LOAD FOLLOW-UP CONTROL OF BOILING WATER TYPE NUCLEAR POWER GENERATION PLANT 失效
公开(公告)号：JPS63279199A
公开(公告)日：1988-11-16
申请号：JP11346487
申请日：1987-05-12
申请人： HITACHI LTD
发明人： YAGI HIROYUKI , HIROSE MASAO , MIKI MINORU
IPC分类号： G21D3/12
摘要： PURPOSE:To achieve a load follow-up operation without lowering generation efficiency so much in a boiling water type nuclear reactor of natural circulation, by providing a bypass line to a condenser via a bypass valve for output control and a feed heater from a main steam pipe. CONSTITUTION:In a power generation plant which uses a boiling water type nuclear reactor 1 (of natural circulation) having no control means of a core flow rate, steam of a main steam pipe 13 is sent to a turbine 3 via a steam control valve 10 and circulated to the reactor 1 via a pump 4, a water feed pipe 36 and the like after being condensated with a condenser 2. A turbine bypass line 12A is provided to send steam of the main steam pipe 13 to the condenser 2 via a turbine bypass valve 12 for output control and a feed heater 35. The opening of the valve 12 is adjusted according to a load follow-up signal 20, thereby allowing a load follow-up control without affecting a nuclear reactor pressure remarkably. Steam sent to the condenser 2 through the valve 12 restores heat energy to feed water with the feed heater 35 in the course thereof, thereby preventing the lowering of generation efficiency.

8. 发明专利

JPS62210746A DATA RESENDING SYSTEM 失效
公开(公告)号：JPS62210746A
公开(公告)日：1987-09-16
申请号：JP5399186
申请日：1986-03-12
申请人： HITACHI LTD
发明人： NAKAMURA TSUTOMU , FUJIKURA NOBUYUKI , SHINNAI KOSUKE , HAGIWARA MASAYOSHI , SASAKI RYOICHI , YAGI HIROYUKI
IPC分类号： H04L1/16
摘要： PURPOSE:To prevent a throughput or efficiency in a transmission line from being lowered, by resending only a frame in which an error is generated normally, and resending all the frames after the frame in which the error is generated, when the number of erroneous frames exceed a regulated value continuously. CONSTITUTION:In a normal operation, only the erroneous frame is resent, and also at the same time, a system is regulated by a Selective Repeat ARQ possible to perform plural number of resending requests. And when the number of continuous erroneous frames exceed the regulated value, all of the frames after the frame in which the error is generated, are resent by logic link unit sharing a data link. The system is switched to a Go-Back-N ARQ system, then a resending is performed. In this way, data to be resent is the one that is transmitted by logic links 10-12 sharing a channel, and for example, when the error is generated in the logic link 10 which transmits the data belonging to an application program 7, only the data of the logic link 10 is resent, therefore, it is not necessary to resend the data transmitted by other logic links.

9. 发明专利

JPS61228744A PRIVACY CALL COMMUNICATION SYSTEM 失效
公开(公告)号：JPS61228744A
公开(公告)日：1986-10-11
申请号：JP6897785
申请日：1985-04-03
申请人： HITACHI LTD
发明人： YAGI HIROYUKI , TAKARAGI KAZUO , SASAKI RYOICHI , SHIRAISHI TAKAYOSHI , NAKAMURA TSUTOMU
IPC分类号： H04L9/00 , H04L9/12
摘要： PURPOSE:To attain the processing of encipherment and decoding in high speed by providing a means changing timewise a synchronizing code representing the start/end of a frame being the unit of sent information and a means disabling the mixture of the synchronizing code and the information in other frame. CONSTITUTION:Random number generators 30, 150 and memories 50, 130 are added to a data terminal equipment is a communication line to add the processing such as addition, deletion of the start/end flag sequence of a frame and disabled mixture between the flag sequence and other bit pattern in the frame to data terminal equipments 10, 170. Then a flag sequence corresponding to each flag control number, a bit inserting location and a bit pattern are stored in the memories 50, 130, a signal is sent from the data terminal equipment 10 and received by the data terminal equipment 170, then the flag sequence, bit inserting location and bit pattern in response to the flag control number are inputted.

10. 发明专利

JPS6072006A LOGICAL CIRCUIT DIAGNOSTIC SYSTEM 失效
公开(公告)号：JPS6072006A
公开(公告)日：1985-04-24
申请号：JP17803883
申请日：1983-09-28
申请人： HITACHI LTD
发明人： YAGI HIROYUKI
IPC分类号： G05B23/02
摘要： PURPOSE:To execute exactly and easily a diagnosis by inputting a mimic signal, and diagnosing its output result, with regard to a logical circuit whose diagnosis and quantitative evaluation are difficult. CONSTITUTION:A logical circuit diagnostic system 9 is constituted of a diagnostic result displaying CRT picture 1, a line printer 2, a logical circuit diagnostic device 3 for executing a diagnosis by generating a mimic signal, and a data storage device 4. In this storage device 4, an abnormal pattern, etc. of a logical circuit 6 of an operating device 8 are inputted in advance, a decision of a fact that a data is a mimic signal in the maximum signal generation rate by said diagnostic device 3, and a calculation of the generation probability are executed, and the signal is inputted to the logical circuit 6 through an input processing device 5. This signal is returned to said diagnostic device 4 through an output processing device 7. In this case, whether a signal processing result of the logical circuit 6 is an abnormal processing pattern or not is checked, and displayed on a CRT picture 1, etc.

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