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1. 发明专利

JPS60183759A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60183759A
公开(公告)日：1985-09-19
申请号：JP3856284
申请日：1984-03-02
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： USAMI TAMOTSU , OKUYA KEN , SHIRAI MASAYUKI , YAMAZAKI YASUYUKI , OOTSUKA KANJI , SATOU KAZUYOSHI , KAMATA CHIYOJI , MORISHITA JIYUN , YAMASHITA MICHIO
IPC分类号： H01L23/52 , H01L23/15 , H01L23/373 , H01L23/538
摘要： PURPOSE:To check generation of exfoliation and a crack, etc. at the connecting part of a semiconductor device by a method wherein a main substrate to be fitted with an auxiliary substrate for wiring is formed of a material mainly consisting of silicon carbide. CONSTITUTION:A main substrate 1 to be fitted with an auxiliary substrate 3 for wiring is manufactured of a material mainly consisting of silicon carbide. The coefficient of thermal expansion of the SiC thereof is extremely close by Si, and Si according to matching of the coefficients of thermal expansion of the SiC and like this, adhesion of the auxiliary substrate 3 for wiring to the main substrate 1 is insured without generating problems such as a crack and exfoliation, etc. to be caused according to thermal stress, and reliability is enhanced sharply. Moreover, because, SiC is material having a favorable heat dissipating property, heat generated from semiconductor pellets 5 of the plural number of pieces is transmitted to the main substrate 1 through solder pads 4 and the auxiliary substrate 3 for wiring, and moreover, transmitted mainly to a heat disipating fin 14 through the material mainly consisting of the SiC of the main substrate 1 thereof, and radiated to the periphery through the heat dissipating fin 14.

2. 发明专利

JPS60200558A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60200558A
公开(公告)日：1985-10-11
申请号：JP5610684
申请日：1984-03-26
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： MORISHITA JIYUN , SATOU KAZUYOSHI , KAMATA CHIYOJI , YAMASHITA MICHIO , USAMI TAMOTSU , OKUYA KEN , SHIRAI MASAYUKI , YAMAZAKI YASUYUKI , OOTSUKA KANJI
IPC分类号： H01L25/00 , H01L23/14 , H01L23/15 , H01L23/538
摘要： PURPOSE:To readily perform multiple types by forming a wiring auxiliary substrate on which a semiconductor element is mounted, in a master-slice type structure. CONSTITUTION:A wiring auxiliary substrate 3 is secured through gold-silicon eutectic portion 2 to one surface of a main substrate 1 which forms the base of a semiconductor device. A plurality of semiconductor pellets 5 are connected in flip chip type in opposed state with bump electrodes 4 made of solder on the opposite surface and hence the circuit wiring forming surface of the substrate 3, and electrically connected by the electrodes 4 between the pellets 5 and the wirings of the substrate 3. The substrate 3 is designed in so-called master-slice type. Accordingly, the substrate 3 can incorporate with semiconductor devices of multiple types by altering the wirings to provide advantageous cost.

3. 发明专利

JPS60154643A SEMICONDUCTOR DEVICE 失效
公开(公告)号：JPS60154643A
公开(公告)日：1985-08-14
申请号：JP1017584
申请日：1984-01-25
申请人： HITACHI MICROCUMPUTER ENG , HITACHI LTD
发明人： MORISHITA JIYUN , SATOU KAZUYOSHI
IPC分类号： H01L21/60
摘要： PURPOSE:To facilitate the formation of a flip chip and to increase the density of a semiconductor device by forming a bump for bonding the chip at a pitch different from that of pads for wire bonding on the pads for the wire bonding formed at the prescribed pitch on a substrate. CONSTITUTION:Pads 3 (electrodes) for aluminum wire bonding are formed on an Si semiconductor substrate 2, and an SiO2 layer 4 is formed by sputtering. A connecting layer 5 made, for example, of Cr-Cu-Au alloy is formed on the upside of the pads 3 to connect the contacts of the pads 3 with bumps 6 for bonding a flip-chip. The bumps 6 have different pitch B from the pitch A of the pads 3. Thus, the bumps 6 for bonding the chip do not necessitate to alter the background wirings of a pellet 1, but can be readily arranged on the contacts of the pads 3 through the layer 5.

4. 发明专利

JPS58127350A INSERTING TYPE STAMP 失效
公开(公告)号：JPS58127350A
公开(公告)日：1983-07-29
申请号：JP890182
申请日：1982-01-25
申请人： HITACHI LTD , HITACHI MICROCUMPUTER ENG
发明人： MORISHITA JIYUN , HOSOSAKA HIROSHI
IPC分类号： B41F17/36 , H01L23/00 , H01L23/544
摘要： PURPOSE:To easily realize loading and unloading of inserting mark without lowering marking accuracy by providing a cut-away part to the external frame of inserting part of mark. CONSTITUTION:A holder 2 mounted to a stamp seat 1 is equally divided into an inserting hole 3 and a fixing mark 5 fitting part for fixing system. A cut-away part 4 is provided to the central area of outer frame of holder in both ends in the longitudinal direction of inserting hole 3 in order to make easy the loading and unloading of the inserting mark 6 and 7 is a rubber for buffering. Therefore, an inserting mark 6 can be loaded or unleaded easily by closly accommodating the inserting mark 6 into the inserting hole 3 of the inserting part and utilizing the cut-away part 4. As a result, the inserting part does not require the space for number of characters plus one character and the space for one character can be saved. In addition, accuracy of character arrangement of mark and marking can be improved.

5. 发明专利

JPS6123332A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS6123332A
公开(公告)日：1986-01-31
申请号：JP14237384
申请日：1984-07-11
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： YAMASHITA MICHIO , ENOMOTO MINORU , SATOU KAZUYOSHI , MORISHITA JIYUN
IPC分类号： H01L21/60 , H01L21/66
CPC分类号： H01L22/00 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PURPOSE:To improve operativity of a probe test for a semiconductor device which adopts a flip chip type of face-down bonding, by arranging probe test wiring on a wiring substrate loading a semiconductor chip. CONSTITUTION:Probe test wiring 6 is arranged between two terminals 5A, 5B. For example, by evaporating solders 4C on a motor chip 2 using an evaporating mask, the two terminals 5A, 5B are short-circuited each other. In this state, by doing probe test contacting respective terminals 11A, 11B of a measuring instrument with bonding pads 7A, 7B on the mother chip 2, conducting check on two wirings 8A, 8B is made simultaneously. By doing a wet back process, the solders 4C are made round and soldering bump electrodes 4A, 4B are formed in which the terminals 5A, 5B are separated physically and electrically. In this state, contacting the terminals 11A, 11B of the measuring instrument with the bonding pads 7A, 7B, short circuit check between the two soldering bump electrodes 4A, 4B is done.
摘要翻译：目的：通过在加载半导体芯片的布线基板上布置探针测试布线，提高采用倒装芯片类型的面朝下键合的半导体器件的探针测试的操作性。构成：探头测试布线6布置在两个端子5A，5B之间。例如，通过使用蒸发掩模在电动机芯片2上蒸发焊料4C，两个端子5A，5B彼此短路。在这种状态下，通过在母芯片2上进行探针测试使具有接合焊盘7A，7B的测量仪器的端子11A，11B接触，同时进行两条布线8A，8B的检查。通过进行回湿处理，将焊料4C制成圆形，并且形成端子5A，5B物理和电气分离的焊接凸块电极4A，4B。在这种状态下，使测量仪器的端子11A，11B与接合焊盘7A，7B接触，进行两个焊接凸块电极4A，4B之间的短路检查。

6. 发明专利

JPS60195959A Lead frame and manufacture thereof 失效
标题翻译：引导框架及其制造
公开(公告)号：JPS60195959A
公开(公告)日：1985-10-04
申请号：JP5099584
申请日：1984-03-19
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： TAKEO YOSHIHISA , MORISHITA JIYUN , SATOU KAZUYOSHI
IPC分类号： H01L23/50 , H01L21/48
CPC分类号： H01L21/4839
摘要： PURPOSE:To rapidly and accurately test a product by coupling between lead pins with an insulating material, thereby electrically separating the pins and eliminating the labor of a temporarily mounting on a baby board. CONSTITUTION:A frame 3 is superposed on a conductive plate 1. In this case, the lead pin 2 of the plate 1 is superposed on the frame 3. The superposed body is heated to melt the glass material of the frame 3, then cooled to secure the plate 1 to the frame 3 or the plate 1 is secured to the frame 3 with an insulating adhesive. Then, the plate 1 at the center to the frame 3 is etched. In other words, the plate of the center of the plate 1 is removed by etching, and the pattern is removed by etching according to the desired pattern of the pin 2, and patterned according to the desired pattern of the pin 2. Thus, many pins 2 are coupled with the insulating frame 3 to obtain a lead frame 4.
摘要翻译：目的：通过将引脚与绝缘材料相结合来快速准确地测试产品，从而电气分离引脚，并消除临时安装在婴儿板上的劳动。构成：将框架3重叠在导电板1上。在这种情况下，板1的引导销2重叠在框架3上。叠加体被加热以熔化框架3的玻璃材料，然后冷却至将板1固定到框架3上，或者使用绝缘粘合剂将板1固定到框架3。然后，蚀刻在框架3的中心的板1。换句话说，通过蚀刻去除板1的中心的板，并且根据销2的期望图案通过蚀刻去除图案，并根据销2的期望图案进行图案化。因此，许多引脚2与绝缘框架3耦合以获得引线框架4。

7. 发明专利

JPS59117252A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59117252A
公开(公告)日：1984-07-06
申请号：JP22630882
申请日：1982-12-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MORISHITA JIYUN , SATOU KAZUYOSHI , TAKEO YOSHIHISA
IPC分类号： H01L25/18 , G01R31/26 , H01L21/60 , H01L23/52 , H01L25/065 , H01L25/07
CPC分类号： G01R31/2644 , H01L2224/48091 , H01L2224/48247 , H01L2924/00014
摘要： PURPOSE:To perform tests readily even in the case of high density mounting, by arranging dummy pads for testing at the peripheral part and the like of semiconductor pellets. CONSTITUTION:Pads 4 for bonding are arranged at the central part of a lower semiconductor pellet 1, and pads 5 are arranged at the peripheral part of the pellet. Of these, the pad 5a is used for wire bonding and the pad 5b is used for a probe test. Pads 6 for bonding are provided at the central part of an upper semiconductor pellet 2, and pads 7 for a probe test are provided at the peripheral part of the pellet 2. In this way, the probe test can be performed not by the pads 4 and 6 at the central part, but by the pads 5b and 7b at the peripheral part. Therefore, the testing becomes very easy.
摘要翻译：目的：即使在高密度安装的情况下，也可以通过在半导体颗粒的周边部等配置用于测试的虚拟垫来进行试验。构成：用于接合的焊盘4布置在下半导体颗粒1的中心部分处，并且焊盘5布置在颗粒的周边部分。其中，焊盘5a用于引线接合，并且焊盘5b用于探针测试。在上半导体芯片2的中央部设置用于接合的焊盘6，在芯片2的周边部设置用于探针试验用的焊盘7.以这种方式，探针测试不能由焊盘4 和6处在中心部分，但是通过周边部分处的焊盘5b和7b。因此，测试变得非常容易。

8. 发明专利

JPS59117251A Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：JPS59117251A
公开(公告)日：1984-07-06
申请号：JP22630782
申请日：1982-12-24
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MORISHITA JIYUN , SATOU KAZUYOSHI , NAKANO TETSUO , ENOMOTO MINORU , SEKI MASATOSHI
IPC分类号： H01L25/18 , H01L21/60 , H01L23/52 , H01L25/065 , H01L25/07
CPC分类号： H01L25/0657 , H01L2224/16145 , H01L2224/48091 , H01L2225/0651 , H01L2225/06513 , H01L2225/06527 , H01L2225/06582 , H01L2225/06589 , H01L2924/00014
摘要： PURPOSE:To obtain high reliability, by electrically connecting different kinds of semiconductor pellets made of the same material so that they face each other, thereby preventing the concentration of stress to the connecting points between the semiconductor pellets. CONSTITUTION:An upper semiconductor pellet 2 is connected to a lower semiconductor pellet 1 by connecting bumps 3 in a facing state. The pellets 1 and 2 are made of silicon. The connecting bumps 3 are made of solder. The lower pellet 1 is used for logics, and the upper pellet 2 is a semiconductor integrated circuit for a memory. In this compound pellet structure, the lower semiconductor pellet 1 and the upper semiconductor pellt 2 are made of the same silicon in additon to the high density mounting. Therefore, thermal expansion coefficient is the same, and the concentration of stress to the connecting bumps 3 can be avoided. Breakdown of the connecting state can be prevented, and the high reliability can be obtained.
摘要翻译：目的：为了获得高可靠性，通过将由相同材料制成的不同种类的半导体芯片电连接使得它们彼此面对，从而防止对半导体芯片之间的连接点的应力集中。构成：上半导体芯片2通过以相对的状态连接凸块3而连接到下半导体芯片1。颗粒1和2由硅制成。连接凸块3由焊料制成。下部颗粒1用于逻辑，上部颗粒2是用于存储器的半导体集成电路。在该复合颗粒结构中，除了高密度安装之外，下半导体颗粒1和上半导体薄膜2由相同的硅制成。因此，热膨胀系数相同，能够避免对连接凸块3的应力集中。可以防止连接状态的破坏，可以获得高的可靠性。

9. 发明专利

JPS5966137A Wire bonding method 失效
标题翻译：线接法
公开(公告)号：JPS5966137A
公开(公告)日：1984-04-14
申请号：JP17617982
申请日：1982-10-08
申请人： Hitachi Ltd , Hitachi Micro Comput Eng Ltd
发明人： MORISHITA JIYUN
IPC分类号： H01L21/60
CPC分类号： H01L24/06 , H01L23/50 , H01L2224/05554 , H01L2224/48 , H01L2224/48091 , H01L2224/48245 , H01L2224/48247 , H01L2224/49 , H01L2224/49175 , H01L2224/85 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01082 , H01L2224/78 , H01L2924/00 , H01L2924/00012
摘要： PURPOSE:To reduce the waste of a wire material for wiring, and the number and time of bonding, and to improve the yield of an external appearance and the reliability of a wire bonding method by selectively wire bonding only a bonding pad used for inputting/outputting and a conductive part. CONSTITUTION:A wire 5 is not bonded to unused bonding pads A, E and an inner lead 4 corresponding thereto, but selectively bonded only to bonding pads B, C, D used for inputting/outputting. Since such a selective wire bonding can be readily executed for each type of pellets 1 by using a coordinate recognition of bonding with an RAM system or the like, wire material can be saved, the number of bonding steps and time can be shortened, and the yield of an external appearance and reliability can be improved.
摘要翻译：目的：为了减少用于布线的线材的浪费以及接合的数量和时间，并且通过选择性地仅引线接合用于输入/输出的接合焊盘，并且提高引线接合方法的可靠性，输出和导电部分。构成：电线5不与未使用的接合焊盘A，E和与其对应的内引线4接合，而是仅选择性地结合到用于输入/输出的接合焊盘B，C，D。由于通过使用与RAM系统等的接合的坐标识别，可以容易地对每种类型的粒料1执行这样的选择性线接合，可以节省线材，可以缩短接合步骤和时间的数量，并且可以提高外观和可靠性的产量。

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